~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,146 +1,88 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
1	2	/*
2		- * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
3		- *
4		- * This software is available to you under a choice of one of two
5		- * licenses. You may choose to be licensed under the terms of the GNU
6		- * General Public License (GPL) Version 2, available from the file
7		- * COPYING in the main directory of this source tree, or the
8		- * BSD license below:
9		- *
10		- * Redistribution and use in source and binary forms, with or
11		- * without modification, are permitted provided that the following
12		- * conditions are met:
13		- *
14		- * - Redistributions of source code must retain the above
15		- * copyright notice, this list of conditions and the following
16		- * disclaimer.
17		- *
18		- * - Redistributions in binary form must reproduce the above
19		- * copyright notice, this list of conditions and the following
20		- * disclaimer in the documentation and/or other materials
21		- * provided with the distribution.
22		- *
23		- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24		- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25		- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26		- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27		- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28		- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29		- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30		- * SOFTWARE.
	3	+ * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
31	4	*/
32	5	#ifndef _ENA_ADMIN_H_
33	6	#define _ENA_ADMIN_H_
34	7
	8	+#define ENA_ADMIN_RSS_KEY_PARTS 10
	9	+
35	10	enum ena_admin_aq_opcode {
36		- ENA_ADMIN_CREATE_SQ = 1,
37		-
38		- ENA_ADMIN_DESTROY_SQ = 2,
39		-
40		- ENA_ADMIN_CREATE_CQ = 3,
41		-
42		- ENA_ADMIN_DESTROY_CQ = 4,
43		-
44		- ENA_ADMIN_GET_FEATURE = 8,
45		-
46		- ENA_ADMIN_SET_FEATURE = 9,
47		-
48		- ENA_ADMIN_GET_STATS = 11,
	11	+ ENA_ADMIN_CREATE_SQ = 1,
	12	+ ENA_ADMIN_DESTROY_SQ = 2,
	13	+ ENA_ADMIN_CREATE_CQ = 3,
	14	+ ENA_ADMIN_DESTROY_CQ = 4,
	15	+ ENA_ADMIN_GET_FEATURE = 8,
	16	+ ENA_ADMIN_SET_FEATURE = 9,
	17	+ ENA_ADMIN_GET_STATS = 11,
49	18	};
50	19
51	20	enum ena_admin_aq_completion_status {
52		- ENA_ADMIN_SUCCESS = 0,
53		-
54		- ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
55		-
56		- ENA_ADMIN_BAD_OPCODE = 2,
57		-
58		- ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
59		-
60		- ENA_ADMIN_MALFORMED_REQUEST = 4,
61		-
	21	+ ENA_ADMIN_SUCCESS = 0,
	22	+ ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
	23	+ ENA_ADMIN_BAD_OPCODE = 2,
	24	+ ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
	25	+ ENA_ADMIN_MALFORMED_REQUEST = 4,
62	26	/* Additional status is provided in ACQ entry extended_status */
63		- ENA_ADMIN_ILLEGAL_PARAMETER = 5,
64		-
65		- ENA_ADMIN_UNKNOWN_ERROR = 6,
	27	+ ENA_ADMIN_ILLEGAL_PARAMETER = 5,
	28	+ ENA_ADMIN_UNKNOWN_ERROR = 6,
	29	+ ENA_ADMIN_RESOURCE_BUSY = 7,
66	30	};
67	31
	32	+/* subcommands for the set/get feature admin commands */
68	33	enum ena_admin_aq_feature_id {
69		- ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
70		-
71		- ENA_ADMIN_MAX_QUEUES_NUM = 2,
72		-
73		- ENA_ADMIN_HW_HINTS = 3,
74		-
75		- ENA_ADMIN_RSS_HASH_FUNCTION = 10,
76		-
77		- ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
78		-
79		- ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
80		-
81		- ENA_ADMIN_MTU = 14,
82		-
83		- ENA_ADMIN_RSS_HASH_INPUT = 18,
84		-
85		- ENA_ADMIN_INTERRUPT_MODERATION = 20,
86		-
87		- ENA_ADMIN_AENQ_CONFIG = 26,
88		-
89		- ENA_ADMIN_LINK_CONFIG = 27,
90		-
91		- ENA_ADMIN_HOST_ATTR_CONFIG = 28,
92		-
93		- ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
	34	+ ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
	35	+ ENA_ADMIN_MAX_QUEUES_NUM = 2,
	36	+ ENA_ADMIN_HW_HINTS = 3,
	37	+ ENA_ADMIN_LLQ = 4,
	38	+ ENA_ADMIN_MAX_QUEUES_EXT = 7,
	39	+ ENA_ADMIN_RSS_HASH_FUNCTION = 10,
	40	+ ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
	41	+ ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
	42	+ ENA_ADMIN_MTU = 14,
	43	+ ENA_ADMIN_RSS_HASH_INPUT = 18,
	44	+ ENA_ADMIN_INTERRUPT_MODERATION = 20,
	45	+ ENA_ADMIN_AENQ_CONFIG = 26,
	46	+ ENA_ADMIN_LINK_CONFIG = 27,
	47	+ ENA_ADMIN_HOST_ATTR_CONFIG = 28,
	48	+ ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
94	49	};
95	50
96	51	enum ena_admin_placement_policy_type {
97	52	/* descriptors and headers are in host memory */
98		- ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
99		-
	53	+ ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
100	54	/* descriptors and headers are in device memory (a.k.a Low Latency
101	55	* Queue)
102	56	*/
103		- ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
	57	+ ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
104	58	};
105	59
106	60	enum ena_admin_link_types {
107		- ENA_ADMIN_LINK_SPEED_1G = 0x1,
108		-
109		- ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
110		-
111		- ENA_ADMIN_LINK_SPEED_5G = 0x4,
112		-
113		- ENA_ADMIN_LINK_SPEED_10G = 0x8,
114		-
115		- ENA_ADMIN_LINK_SPEED_25G = 0x10,
116		-
117		- ENA_ADMIN_LINK_SPEED_40G = 0x20,
118		-
119		- ENA_ADMIN_LINK_SPEED_50G = 0x40,
120		-
121		- ENA_ADMIN_LINK_SPEED_100G = 0x80,
122		-
123		- ENA_ADMIN_LINK_SPEED_200G = 0x100,
124		-
125		- ENA_ADMIN_LINK_SPEED_400G = 0x200,
	61	+ ENA_ADMIN_LINK_SPEED_1G = 0x1,
	62	+ ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
	63	+ ENA_ADMIN_LINK_SPEED_5G = 0x4,
	64	+ ENA_ADMIN_LINK_SPEED_10G = 0x8,
	65	+ ENA_ADMIN_LINK_SPEED_25G = 0x10,
	66	+ ENA_ADMIN_LINK_SPEED_40G = 0x20,
	67	+ ENA_ADMIN_LINK_SPEED_50G = 0x40,
	68	+ ENA_ADMIN_LINK_SPEED_100G = 0x80,
	69	+ ENA_ADMIN_LINK_SPEED_200G = 0x100,
	70	+ ENA_ADMIN_LINK_SPEED_400G = 0x200,
126	71	};
127	72
128	73	enum ena_admin_completion_policy_type {
129	74	/* completion queue entry for each sq descriptor */
130		- ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
131		-
	75	+ ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
132	76	/* completion queue entry upon request in sq descriptor */
133		- ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
134		-
	77	+ ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
135	78	/* current queue head pointer is updated in OS memory upon sq
136	79	* descriptor request
137	80	*/
138		- ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
139		-
	81	+ ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
140	82	/* current queue head pointer is updated in OS memory for each sq
141	83	* descriptor
142	84	*/
143		- ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
	85	+ ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
144	86	};
145	87
146	88	/* basic stats return ena_admin_basic_stats while extanded stats return a
..	..	@@ -148,15 +90,15 @@
148	90	* device id
149	91	*/
150	92	enum ena_admin_get_stats_type {
151		- ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
152		-
153		- ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
	93	+ ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
	94	+ ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
	95	+ /* extra HW stats for specific network interface */
	96	+ ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
154	97	};
155	98
156	99	enum ena_admin_get_stats_scope {
157		- ENA_ADMIN_SPECIFIC_QUEUE = 0,
158		-
159		- ENA_ADMIN_ETH_TRAFFIC = 1,
	100	+ ENA_ADMIN_SPECIFIC_QUEUE = 0,
	101	+ ENA_ADMIN_ETH_TRAFFIC = 1,
160	102	};
161	103
162	104	struct ena_admin_aq_common_desc {
..	..	@@ -227,7 +169,9 @@
227	169
228	170	u16 extended_status;
229	171
230		- /* serves as a hint what AQ entries can be revoked */
	172	+ /* indicates to the driver which AQ entry has been consumed by the
	173	+ * device and could be reused
	174	+ */
231	175	u16 sq_head_indx;
232	176	};
233	177
..	..	@@ -271,8 +215,8 @@
271	215	*/
272	216	u8 sq_caps_3;
273	217
274		- /* associated completion queue id. This CQ must be created prior to
275		- * SQ creation
	218	+ /* associated completion queue id. This CQ must be created prior to SQ
	219	+ * creation
276	220	*/
277	221	u16 cq_idx;
278	222
..	..	@@ -296,9 +240,8 @@
296	240	};
297	241
298	242	enum ena_admin_sq_direction {
299		- ENA_ADMIN_SQ_DIRECTION_TX = 1,
300		-
301		- ENA_ADMIN_SQ_DIRECTION_RX = 2,
	243	+ ENA_ADMIN_SQ_DIRECTION_TX = 1,
	244	+ ENA_ADMIN_SQ_DIRECTION_RX = 2,
302	245	};
303	246
304	247	struct ena_admin_acq_create_sq_resp_desc {
..	..	@@ -412,7 +355,7 @@
412	355	u16 queue_idx;
413	356
414	357	/* device id, value 0xFFFF means mine. only privileged device can get
415		- * stats of other device
	358	+ * stats of other device
416	359	*/
417	360	u16 device_id;
418	361	};
..	..	@@ -438,12 +381,49 @@
438	381	u32 rx_drops_low;
439	382
440	383	u32 rx_drops_high;
	384	+
	385	+ u32 tx_drops_low;
	386	+
	387	+ u32 tx_drops_high;
	388	+};
	389	+
	390	+/* ENI Statistics Command. */
	391	+struct ena_admin_eni_stats {
	392	+ /* The number of packets shaped due to inbound aggregate BW
	393	+ * allowance being exceeded
	394	+ */
	395	+ u64 bw_in_allowance_exceeded;
	396	+
	397	+ /* The number of packets shaped due to outbound aggregate BW
	398	+ * allowance being exceeded
	399	+ */
	400	+ u64 bw_out_allowance_exceeded;
	401	+
	402	+ /* The number of packets shaped due to PPS allowance being exceeded */
	403	+ u64 pps_allowance_exceeded;
	404	+
	405	+ /* The number of packets shaped due to connection tracking
	406	+ * allowance being exceeded and leading to failure in establishment
	407	+ * of new connections
	408	+ */
	409	+ u64 conntrack_allowance_exceeded;
	410	+
	411	+ /* The number of packets shaped due to linklocal packet rate
	412	+ * allowance being exceeded
	413	+ */
	414	+ u64 linklocal_allowance_exceeded;
441	415	};
442	416
443	417	struct ena_admin_acq_get_stats_resp {
444	418	struct ena_admin_acq_common_desc acq_common_desc;
445	419
446		- struct ena_admin_basic_stats basic_stats;
	420	+ union {
	421	+ u64 raw[7];
	422	+
	423	+ struct ena_admin_basic_stats basic_stats;
	424	+
	425	+ struct ena_admin_eni_stats eni_stats;
	426	+ } u;
447	427	};
448	428
449	429	struct ena_admin_get_set_feature_common_desc {
..	..	@@ -456,7 +436,13 @@
456	436	/* as appears in ena_admin_aq_feature_id */
457	437	u8 feature_id;
458	438
459		- u16 reserved16;
	439	+ /* The driver specifies the max feature version it supports and the
	440	+ * device responds with the currently supported feature version. The
	441	+ * field is zero based
	442	+ */
	443	+ u8 feature_version;
	444	+
	445	+ u8 reserved8;
460	446	};
461	447
462	448	struct ena_admin_device_attr_feature_desc {
..	..	@@ -464,7 +450,9 @@
464	450
465	451	u32 device_version;
466	452
467		- /* bitmap of ena_admin_aq_feature_id */
	453	+ /* bitmap of ena_admin_aq_feature_id, which represents supported
	454	+ * subcommands for the set/get feature admin commands.
	455	+ */
468	456	u32 supported_features;
469	457
470	458	u32 reserved3;
..	..	@@ -483,8 +471,149 @@
483	471	u32 max_mtu;
484	472	};
485	473
	474	+enum ena_admin_llq_header_location {
	475	+ /* header is in descriptor list */
	476	+ ENA_ADMIN_INLINE_HEADER = 1,
	477	+ /* header in a separate ring, implies 16B descriptor list entry */
	478	+ ENA_ADMIN_HEADER_RING = 2,
	479	+};
	480	+
	481	+enum ena_admin_llq_ring_entry_size {
	482	+ ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
	483	+ ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
	484	+ ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
	485	+};
	486	+
	487	+enum ena_admin_llq_num_descs_before_header {
	488	+ ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
	489	+ ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
	490	+ ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
	491	+ ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
	492	+ ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
	493	+};
	494	+
	495	+/* packet descriptor list entry always starts with one or more descriptors,
	496	+ * followed by a header. The rest of the descriptors are located in the
	497	+ * beginning of the subsequent entry. Stride refers to how the rest of the
	498	+ * descriptors are placed. This field is relevant only for inline header
	499	+ * mode
	500	+ */
	501	+enum ena_admin_llq_stride_ctrl {
	502	+ ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
	503	+ ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
	504	+};
	505	+
	506	+enum ena_admin_accel_mode_feat {
	507	+ ENA_ADMIN_DISABLE_META_CACHING = 0,
	508	+ ENA_ADMIN_LIMIT_TX_BURST = 1,
	509	+};
	510	+
	511	+struct ena_admin_accel_mode_get {
	512	+ /* bit field of enum ena_admin_accel_mode_feat */
	513	+ u16 supported_flags;
	514	+
	515	+ /* maximum burst size between two doorbells. The size is in bytes */
	516	+ u16 max_tx_burst_size;
	517	+};
	518	+
	519	+struct ena_admin_accel_mode_set {
	520	+ /* bit field of enum ena_admin_accel_mode_feat */
	521	+ u16 enabled_flags;
	522	+
	523	+ u16 reserved;
	524	+};
	525	+
	526	+struct ena_admin_accel_mode_req {
	527	+ union {
	528	+ u32 raw[2];
	529	+
	530	+ struct ena_admin_accel_mode_get get;
	531	+
	532	+ struct ena_admin_accel_mode_set set;
	533	+ } u;
	534	+};
	535	+
	536	+struct ena_admin_feature_llq_desc {
	537	+ u32 max_llq_num;
	538	+
	539	+ u32 max_llq_depth;
	540	+
	541	+ /* specify the header locations the device supports. bitfield of enum
	542	+ * ena_admin_llq_header_location.
	543	+ */
	544	+ u16 header_location_ctrl_supported;
	545	+
	546	+ /* the header location the driver selected to use. */
	547	+ u16 header_location_ctrl_enabled;
	548	+
	549	+ /* if inline header is specified - this is the size of descriptor list
	550	+ * entry. If header in a separate ring is specified - this is the size
	551	+ * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
	552	+ * specify the entry sizes the device supports
	553	+ */
	554	+ u16 entry_size_ctrl_supported;
	555	+
	556	+ /* the entry size the driver selected to use. */
	557	+ u16 entry_size_ctrl_enabled;
	558	+
	559	+ /* valid only if inline header is specified. First entry associated with
	560	+ * the packet includes descriptors and header. Rest of the entries
	561	+ * occupied by descriptors. This parameter defines the max number of
	562	+ * descriptors precedding the header in the first entry. The field is
	563	+ * bitfield of enum ena_admin_llq_num_descs_before_header and specify
	564	+ * the values the device supports
	565	+ */
	566	+ u16 desc_num_before_header_supported;
	567	+
	568	+ /* the desire field the driver selected to use */
	569	+ u16 desc_num_before_header_enabled;
	570	+
	571	+ /* valid only if inline was chosen. bitfield of enum
	572	+ * ena_admin_llq_stride_ctrl
	573	+ */
	574	+ u16 descriptors_stride_ctrl_supported;
	575	+
	576	+ /* the stride control the driver selected to use */
	577	+ u16 descriptors_stride_ctrl_enabled;
	578	+
	579	+ /* reserved */
	580	+ u32 reserved1;
	581	+
	582	+ /* accelerated low latency queues requirement. driver needs to
	583	+ * support those requirements in order to use accelerated llq
	584	+ */
	585	+ struct ena_admin_accel_mode_req accel_mode;
	586	+};
	587	+
	588	+struct ena_admin_queue_ext_feature_fields {
	589	+ u32 max_tx_sq_num;
	590	+
	591	+ u32 max_tx_cq_num;
	592	+
	593	+ u32 max_rx_sq_num;
	594	+
	595	+ u32 max_rx_cq_num;
	596	+
	597	+ u32 max_tx_sq_depth;
	598	+
	599	+ u32 max_tx_cq_depth;
	600	+
	601	+ u32 max_rx_sq_depth;
	602	+
	603	+ u32 max_rx_cq_depth;
	604	+
	605	+ u32 max_tx_header_size;
	606	+
	607	+ /* Maximum Descriptors number, including meta descriptor, allowed for a
	608	+ * single Tx packet
	609	+ */
	610	+ u16 max_per_packet_tx_descs;
	611	+
	612	+ /* Maximum Descriptors number allowed for a single Rx packet */
	613	+ u16 max_per_packet_rx_descs;
	614	+};
	615	+
486	616	struct ena_admin_queue_feature_desc {
487		- /* including LLQs */
488	617	u32 max_sq_num;
489	618
490	619	u32 max_sq_depth;
..	..	@@ -493,14 +622,14 @@
493	622
494	623	u32 max_cq_depth;
495	624
496		- u32 max_llq_num;
	625	+ u32 max_legacy_llq_num;
497	626
498		- u32 max_llq_depth;
	627	+ u32 max_legacy_llq_depth;
499	628
500	629	u32 max_header_size;
501	630
502		- /* Maximum Descriptors number, including meta descriptor, allowed for
503		- * a single Tx packet
	631	+ /* Maximum Descriptors number, including meta descriptor, allowed for a
	632	+ * single Tx packet
504	633	*/
505	634	u16 max_packet_tx_descs;
506	635
..	..	@@ -583,17 +712,16 @@
583	712	};
584	713
585	714	enum ena_admin_hash_functions {
586		- ENA_ADMIN_TOEPLITZ = 1,
587		-
588		- ENA_ADMIN_CRC32 = 2,
	715	+ ENA_ADMIN_TOEPLITZ = 1,
	716	+ ENA_ADMIN_CRC32 = 2,
589	717	};
590	718
591	719	struct ena_admin_feature_rss_flow_hash_control {
592		- u32 keys_num;
	720	+ u32 key_parts;
593	721
594	722	u32 reserved;
595	723
596		- u32 key[10];
	724	+ u32 key[ENA_ADMIN_RSS_KEY_PARTS];
597	725	};
598	726
599	727	struct ena_admin_feature_rss_flow_hash_function {
..	..	@@ -611,50 +739,35 @@
611	739
612	740	/* RSS flow hash protocols */
613	741	enum ena_admin_flow_hash_proto {
614		- ENA_ADMIN_RSS_TCP4 = 0,
615		-
616		- ENA_ADMIN_RSS_UDP4 = 1,
617		-
618		- ENA_ADMIN_RSS_TCP6 = 2,
619		-
620		- ENA_ADMIN_RSS_UDP6 = 3,
621		-
622		- ENA_ADMIN_RSS_IP4 = 4,
623		-
624		- ENA_ADMIN_RSS_IP6 = 5,
625		-
626		- ENA_ADMIN_RSS_IP4_FRAG = 6,
627		-
628		- ENA_ADMIN_RSS_NOT_IP = 7,
629		-
	742	+ ENA_ADMIN_RSS_TCP4 = 0,
	743	+ ENA_ADMIN_RSS_UDP4 = 1,
	744	+ ENA_ADMIN_RSS_TCP6 = 2,
	745	+ ENA_ADMIN_RSS_UDP6 = 3,
	746	+ ENA_ADMIN_RSS_IP4 = 4,
	747	+ ENA_ADMIN_RSS_IP6 = 5,
	748	+ ENA_ADMIN_RSS_IP4_FRAG = 6,
	749	+ ENA_ADMIN_RSS_NOT_IP = 7,
630	750	/* TCPv6 with extension header */
631		- ENA_ADMIN_RSS_TCP6_EX = 8,
632		-
	751	+ ENA_ADMIN_RSS_TCP6_EX = 8,
633	752	/* IPv6 with extension header */
634		- ENA_ADMIN_RSS_IP6_EX = 9,
635		-
636		- ENA_ADMIN_RSS_PROTO_NUM = 16,
	753	+ ENA_ADMIN_RSS_IP6_EX = 9,
	754	+ ENA_ADMIN_RSS_PROTO_NUM = 16,
637	755	};
638	756
639	757	/* RSS flow hash fields */
640	758	enum ena_admin_flow_hash_fields {
641	759	/* Ethernet Dest Addr */
642		- ENA_ADMIN_RSS_L2_DA = BIT(0),
643		-
	760	+ ENA_ADMIN_RSS_L2_DA = BIT(0),
644	761	/* Ethernet Src Addr */
645		- ENA_ADMIN_RSS_L2_SA = BIT(1),
646		-
	762	+ ENA_ADMIN_RSS_L2_SA = BIT(1),
647	763	/* ipv4/6 Dest Addr */
648		- ENA_ADMIN_RSS_L3_DA = BIT(2),
649		-
	764	+ ENA_ADMIN_RSS_L3_DA = BIT(2),
650	765	/* ipv4/6 Src Addr */
651		- ENA_ADMIN_RSS_L3_SA = BIT(3),
652		-
	766	+ ENA_ADMIN_RSS_L3_SA = BIT(3),
653	767	/* tcp/udp Dest Port */
654		- ENA_ADMIN_RSS_L4_DP = BIT(4),
655		-
	768	+ ENA_ADMIN_RSS_L4_DP = BIT(4),
656	769	/* tcp/udp Src Port */
657		- ENA_ADMIN_RSS_L4_SP = BIT(5),
	770	+ ENA_ADMIN_RSS_L4_SP = BIT(5),
658	771	};
659	772
660	773	struct ena_admin_proto_input {
..	..	@@ -693,15 +806,13 @@
693	806	};
694	807
695	808	enum ena_admin_os_type {
696		- ENA_ADMIN_OS_LINUX = 1,
697		-
698		- ENA_ADMIN_OS_WIN = 2,
699		-
700		- ENA_ADMIN_OS_DPDK = 3,
701		-
702		- ENA_ADMIN_OS_FREEBSD = 4,
703		-
704		- ENA_ADMIN_OS_IPXE = 5,
	809	+ ENA_ADMIN_OS_LINUX = 1,
	810	+ ENA_ADMIN_OS_WIN = 2,
	811	+ ENA_ADMIN_OS_DPDK = 3,
	812	+ ENA_ADMIN_OS_FREEBSD = 4,
	813	+ ENA_ADMIN_OS_IPXE = 5,
	814	+ ENA_ADMIN_OS_ESXI = 6,
	815	+ ENA_ADMIN_OS_GROUPS_NUM = 6,
705	816	};
706	817
707	818	struct ena_admin_host_info {
..	..	@@ -723,11 +834,36 @@
723	834	/* 7:0 : major
724	835	* 15:8 : minor
725	836	* 23:16 : sub_minor
	837	+ * 31:24 : module_type
726	838	*/
727	839	u32 driver_version;
728	840
729	841	/* features bitmap */
730		- u32 supported_network_features[4];
	842	+ u32 supported_network_features[2];
	843	+
	844	+ /* ENA spec version of driver */
	845	+ u16 ena_spec_version;
	846	+
	847	+ /* ENA device's Bus, Device and Function
	848	+ * 2:0 : function
	849	+ * 7:3 : device
	850	+ * 15:8 : bus
	851	+ */
	852	+ u16 bdf;
	853	+
	854	+ /* Number of CPUs */
	855	+ u16 num_cpus;
	856	+
	857	+ u16 reserved;
	858	+
	859	+ /* 0 : reserved
	860	+ * 1 : rx_offset
	861	+ * 2 : interrupt_moderation
	862	+ * 3 : rx_buf_mirroring
	863	+ * 4 : rss_configurable_function_key
	864	+ * 31:5 : reserved
	865	+ */
	866	+ u32 driver_supported_features;
731	867	};
732	868
733	869	struct ena_admin_rss_ind_table_entry {
..	..	@@ -792,6 +928,19 @@
792	928	u32 raw[11];
793	929	};
794	930
	931	+struct ena_admin_queue_ext_feature_desc {
	932	+ /* version */
	933	+ u8 version;
	934	+
	935	+ u8 reserved1[3];
	936	+
	937	+ union {
	938	+ struct ena_admin_queue_ext_feature_fields max_queue_ext;
	939	+
	940	+ u32 raw[10];
	941	+ };
	942	+};
	943	+
795	944	struct ena_admin_get_feat_resp {
796	945	struct ena_admin_acq_common_desc acq_common_desc;
797	946
..	..	@@ -800,7 +949,11 @@
800	949
801	950	struct ena_admin_device_attr_feature_desc dev_attr;
802	951
	952	+ struct ena_admin_feature_llq_desc llq;
	953	+
803	954	struct ena_admin_queue_feature_desc max_queue;
	955	+
	956	+ struct ena_admin_queue_ext_feature_desc max_queue_ext;
804	957
805	958	struct ena_admin_feature_aenq_desc aenq;
806	959
..	..	@@ -847,6 +1000,9 @@
847	1000
848	1001	/* rss indirection table */
849	1002	struct ena_admin_feature_rss_ind_table ind_table;
	1003	+
	1004	+ /* LLQ configuration */
	1005	+ struct ena_admin_feature_llq_desc llq;
850	1006	} u;
851	1007	};
852	1008
..	..	@@ -861,9 +1017,11 @@
861	1017	struct ena_admin_aenq_common_desc {
862	1018	u16 group;
863	1019
864		- u16 syndrom;
	1020	+ u16 syndrome;
865	1021
866		- /* 0 : phase */
	1022	+ /* 0 : phase
	1023	+ * 7:1 : reserved - MBZ
	1024	+ */
867	1025	u8 flags;
868	1026
869	1027	u8 reserved1[3];
..	..	@@ -875,25 +1033,18 @@
875	1033
876	1034	/* asynchronous event notification groups */
877	1035	enum ena_admin_aenq_group {
878		- ENA_ADMIN_LINK_CHANGE = 0,
879		-
880		- ENA_ADMIN_FATAL_ERROR = 1,
881		-
882		- ENA_ADMIN_WARNING = 2,
883		-
884		- ENA_ADMIN_NOTIFICATION = 3,
885		-
886		- ENA_ADMIN_KEEP_ALIVE = 4,
887		-
888		- ENA_ADMIN_AENQ_GROUPS_NUM = 5,
	1036	+ ENA_ADMIN_LINK_CHANGE = 0,
	1037	+ ENA_ADMIN_FATAL_ERROR = 1,
	1038	+ ENA_ADMIN_WARNING = 2,
	1039	+ ENA_ADMIN_NOTIFICATION = 3,
	1040	+ ENA_ADMIN_KEEP_ALIVE = 4,
	1041	+ ENA_ADMIN_AENQ_GROUPS_NUM = 5,
889	1042	};
890	1043
891		-enum ena_admin_aenq_notification_syndrom {
892		- ENA_ADMIN_SUSPEND = 0,
893		-
894		- ENA_ADMIN_RESUME = 1,
895		-
896		- ENA_ADMIN_UPDATE_HINTS = 2,
	1044	+enum ena_admin_aenq_notification_syndrome {
	1045	+ ENA_ADMIN_SUSPEND = 0,
	1046	+ ENA_ADMIN_RESUME = 1,
	1047	+ ENA_ADMIN_UPDATE_HINTS = 2,
897	1048	};
898	1049
899	1050	struct ena_admin_aenq_entry {
..	..	@@ -916,6 +1067,10 @@
916	1067	u32 rx_drops_low;
917	1068
918	1069	u32 rx_drops_high;
	1070	+
	1071	+ u32 tx_drops_low;
	1072	+
	1073	+ u32 tx_drops_high;
919	1074	};
920	1075
921	1076	struct ena_admin_ena_mmio_req_read_less_resp {
..	..	@@ -928,27 +1083,27 @@
928	1083	};
929	1084
930	1085	/* aq_common_desc */
931		-#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
932		-#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
933		-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
934		-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
935		-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
936		-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
	1086	+#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
	1087	+#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
	1088	+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
	1089	+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
	1090	+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
	1091	+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
937	1092
938	1093	/* sq */
939		-#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
940		-#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
	1094	+#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
	1095	+#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
941	1096
942	1097	/* acq_common_desc */
943		-#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
944		-#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
	1098	+#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
	1099	+#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
945	1100
946	1101	/* aq_create_sq_cmd */
947		-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
948		-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
949		-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
950		-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
951		-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
	1102	+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
	1103	+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
	1104	+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
	1105	+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
	1106	+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
952	1107	#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
953	1108
954	1109	/* aq_create_cq_cmd */
..	..	@@ -957,12 +1112,12 @@
957	1112	#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
958	1113
959	1114	/* get_set_feature_common_desc */
960		-#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
	1115	+#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
961	1116
962	1117	/* get_feature_link_desc */
963		-#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
964		-#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
965		-#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
	1118	+#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
	1119	+#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
	1120	+#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
966	1121
967	1122	/* feature_offload_desc */
968	1123	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
..	..	@@ -974,19 +1129,19 @@
974	1129	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
975	1130	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
976	1131	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
977		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
978		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
979		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
980		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
981		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
982		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
	1132	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
	1133	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
	1134	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
	1135	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
	1136	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
	1137	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
983	1138	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
984	1139	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
985	1140	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
986	1141	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
987	1142	#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
988		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
989		-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
	1143	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
	1144	+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
990	1145
991	1146	/* feature_rss_flow_hash_function */
992	1147	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
..	..	@@ -994,25 +1149,40 @@
994	1149
995	1150	/* feature_rss_flow_hash_input */
996	1151	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
997		-#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
	1152	+#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
998	1153	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
999		-#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
	1154	+#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1000	1155	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1001	1156	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1002	1157	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1003	1158	#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1004	1159
1005	1160	/* host_info */
1006		-#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1007		-#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1008		-#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1009		-#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1010		-#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
	1161	+#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
	1162	+#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
	1163	+#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
	1164	+#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
	1165	+#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
	1166	+#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
	1167	+#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
	1168	+#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
	1169	+#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
	1170	+#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
	1171	+#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
	1172	+#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
	1173	+#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
	1174	+#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
	1175	+#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
	1176	+#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
	1177	+#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
	1178	+#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
	1179	+#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
	1180	+#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1011	1181
1012	1182	/* aenq_common_desc */
1013		-#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
	1183	+#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1014	1184
1015	1185	/* aenq_link_change_desc */
1016		-#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
	1186	+#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1017	1187
1018		-#endif /_ENA_ADMIN_H_ /
	1188	+#endif /* _ENA_ADMIN_H_ */