add REDIRECT

hc

2024-10-09 05e59e5fb0064c97a1c10921ecd549f2d4a58565

 kernel/arch/sh/mm/Kconfig
..
..
@@ -1,9 +1,6 @@
1
1
 # SPDX-License-Identifier: GPL-2.0
2
2
 menu "Memory management options"
3
3
 
4
-config QUICKLIST
5
-	def_bool y
6
-
7
4
 config MMU
8
5
         bool "Support for memory management hardware"
9
6
 	depends on !CPU_SH2
..
..
@@ -18,8 +15,7 @@
18
15
 
19
16
 config PAGE_OFFSET
20
17
 	hex
21
-	default "0x80000000" if MMU && SUPERH32
22
-	default "0x20000000" if MMU && SUPERH64
18
+	default "0x80000000" if MMU
23
19
 	default "0x00000000"
24
20
 
25
21
 config FORCE_MAX_ZONEORDER
..
..
@@ -48,7 +44,7 @@
48
44
 config MEMORY_START
49
45
 	hex "Physical memory start address"
50
46
 	default "0x08000000"
51
-	---help---
47
+	help
52
48
 	  Computers built with Hitachi SuperH processors always
53
49
 	  map the ROM starting at address zero.  But the processor
54
50
 	  does not specify the range that RAM takes.
..
..
@@ -75,12 +71,11 @@
75
71
 
76
72
 config 29BIT
77
73
 	def_bool !32BIT
78
-	depends on SUPERH32
79
74
 	select UNCACHED_MAPPING
80
75
 
81
76
 config 32BIT
82
77
 	bool
83
-	default y if CPU_SH5 || !MMU
78
+	default !MMU
84
79
 
85
80
 config PMB
86
81
 	bool "Support 32-bit physical addressing through PMB"
..
..
@@ -155,7 +150,7 @@
155
150
 
156
151
 config IOREMAP_FIXED
157
152
        def_bool y
158
-       depends on X2TLB || SUPERH64
153
+       depends on X2TLB
159
154
 
160
155
 config UNCACHED_MAPPING
161
156
 	bool
..
..
@@ -187,7 +182,7 @@
187
182
 
188
183
 config PAGE_SIZE_64KB
189
184
 	bool "64kB"
190
-	depends on !MMU || CPU_SH4 || CPU_SH5
185
+	depends on !MMU || CPU_SH4
191
186
 	help
192
187
 	  This enables support for 64kB pages, possible on all SH-4
193
188
 	  CPUs and later.
..
..
@@ -219,10 +214,6 @@
219
214
 	bool "64MB"
220
215
 	depends on X2TLB
221
216
 
222
-config HUGETLB_PAGE_SIZE_512MB
223
-	bool "512MB"
224
-	depends on CPU_SH5
225
-
226
217
 endchoice
227
218
 
228
219
 config SCHED_MC
..
..
@@ -245,7 +236,7 @@
245
236
 
246
237
 choice
247
238
 	prompt "Cache mode"
248
-	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
239
+	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
249
240
 	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
250
241
 
251
242
 config CACHE_WRITEBACK