.. | .. |
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86 | 86 | "refclk-frequency", &clock_rate); |
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87 | 87 | if (i) { |
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88 | 88 | dev_err(dev, "No UCTL \"refclk-frequency\"\n"); |
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| 89 | + of_node_put(uctl_node); |
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89 | 90 | goto exit; |
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90 | 91 | } |
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91 | 92 | i = of_property_read_string(uctl_node, |
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92 | 93 | "refclk-type", &clock_type); |
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93 | | - |
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| 94 | + of_node_put(uctl_node); |
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94 | 95 | if (!i && strcmp("crystal", clock_type) == 0) |
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95 | 96 | is_crystal_clock = true; |
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96 | 97 | } |
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.. | .. |
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141 | 142 | default: |
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142 | 143 | pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n", |
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143 | 144 | clock_rate); |
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144 | | - /* Fall through */ |
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| 145 | + fallthrough; |
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145 | 146 | case 12000000: |
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146 | 147 | clk_rst_ctl.s.p_refclk_div = 0; |
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147 | 148 | break; |
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.. | .. |
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442 | 443 | } |
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443 | 444 | device_initcall(octeon_rng_device_init); |
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444 | 445 | |
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445 | | -const struct of_device_id octeon_ids[] __initconst = { |
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| 446 | +static const struct of_device_id octeon_ids[] __initconst = { |
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446 | 447 | { .compatible = "simple-bus", }, |
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447 | 448 | { .compatible = "cavium,octeon-6335-uctl", }, |
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448 | 449 | { .compatible = "cavium,octeon-5750-usbn", }, |
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.. | .. |
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458 | 459 | return !OCTEON_IS_MODEL(OCTEON_CN52XX) && |
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459 | 460 | !OCTEON_IS_MODEL(OCTEON_CN6XXX) && |
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460 | 461 | !OCTEON_IS_MODEL(OCTEON_CN56XX); |
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| 462 | +} |
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| 463 | + |
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| 464 | +static bool __init octeon_has_fixed_link(int ipd_port) |
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| 465 | +{ |
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| 466 | + switch (cvmx_sysinfo_get()->board_type) { |
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| 467 | + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: |
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| 468 | + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: |
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| 469 | + case CVMX_BOARD_TYPE_CN3020_EVB_HS5: |
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| 470 | + case CVMX_BOARD_TYPE_CUST_NB5: |
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| 471 | + case CVMX_BOARD_TYPE_EBH3100: |
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| 472 | + /* Port 1 on these boards is always gigabit. */ |
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| 473 | + return ipd_port == 1; |
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| 474 | + case CVMX_BOARD_TYPE_BBGW_REF: |
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| 475 | + /* Ports 0 and 1 connect to the switch. */ |
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| 476 | + return ipd_port == 0 || ipd_port == 1; |
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| 477 | + } |
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| 478 | + return false; |
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461 | 479 | } |
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462 | 480 | |
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463 | 481 | static void __init octeon_fdt_set_phy(int eth, int phy_addr) |
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.. | .. |
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588 | 606 | fdt_nop_node(initial_boot_params, node); |
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589 | 607 | } |
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590 | 608 | |
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| 609 | +static void __init _octeon_rx_tx_delay(int eth, int rx_delay, int tx_delay) |
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| 610 | +{ |
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| 611 | + fdt_setprop_inplace_cell(initial_boot_params, eth, "rx-delay", |
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| 612 | + rx_delay); |
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| 613 | + fdt_setprop_inplace_cell(initial_boot_params, eth, "tx-delay", |
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| 614 | + tx_delay); |
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| 615 | +} |
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| 616 | + |
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| 617 | +static void __init octeon_rx_tx_delay(int eth, int iface, int port) |
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| 618 | +{ |
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| 619 | + switch (cvmx_sysinfo_get()->board_type) { |
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| 620 | + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: |
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| 621 | + if (iface == 0) { |
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| 622 | + if (port == 0) { |
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| 623 | + /* |
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| 624 | + * Boards with gigabit WAN ports need a |
---|
| 625 | + * different setting that is compatible with |
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| 626 | + * 100 Mbit settings |
---|
| 627 | + */ |
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| 628 | + _octeon_rx_tx_delay(eth, 0xc, 0x0c); |
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| 629 | + return; |
---|
| 630 | + } else if (port == 1) { |
---|
| 631 | + /* Different config for switch port. */ |
---|
| 632 | + _octeon_rx_tx_delay(eth, 0x0, 0x0); |
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| 633 | + return; |
---|
| 634 | + } |
---|
| 635 | + } |
---|
| 636 | + break; |
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| 637 | + case CVMX_BOARD_TYPE_UBNT_E100: |
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| 638 | + if (iface == 0 && port <= 2) { |
---|
| 639 | + _octeon_rx_tx_delay(eth, 0x0, 0x10); |
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| 640 | + return; |
---|
| 641 | + } |
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| 642 | + break; |
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| 643 | + } |
---|
| 644 | + fdt_nop_property(initial_boot_params, eth, "rx-delay"); |
---|
| 645 | + fdt_nop_property(initial_boot_params, eth, "tx-delay"); |
---|
| 646 | +} |
---|
| 647 | + |
---|
591 | 648 | static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) |
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592 | 649 | { |
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593 | 650 | char name_buffer[20]; |
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594 | 651 | int eth; |
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595 | 652 | int phy_addr; |
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596 | 653 | int ipd_port; |
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| 654 | + int fixed_link; |
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597 | 655 | |
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598 | 656 | snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); |
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599 | 657 | eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); |
---|
.. | .. |
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611 | 669 | |
---|
612 | 670 | phy_addr = cvmx_helper_board_get_mii_address(ipd_port); |
---|
613 | 671 | octeon_fdt_set_phy(eth, phy_addr); |
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| 672 | + |
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| 673 | + fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link"); |
---|
| 674 | + if (fixed_link < 0) |
---|
| 675 | + WARN_ON(octeon_has_fixed_link(ipd_port)); |
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| 676 | + else if (!octeon_has_fixed_link(ipd_port)) |
---|
| 677 | + fdt_nop_node(initial_boot_params, fixed_link); |
---|
| 678 | + octeon_rx_tx_delay(eth, i, p); |
---|
614 | 679 | } |
---|
615 | 680 | |
---|
616 | 681 | static void __init octeon_fdt_pip_iface(int pip, int idx) |
---|
.. | .. |
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1054 | 1119 | new_f[0] = cpu_to_be32(48000000); |
---|
1055 | 1120 | fdt_setprop_inplace(initial_boot_params, usbn, |
---|
1056 | 1121 | "refclk-frequency", new_f, sizeof(new_f)); |
---|
1057 | | - /* Fall through ...*/ |
---|
| 1122 | + fallthrough; |
---|
1058 | 1123 | case USB_CLOCK_TYPE_REF_12: |
---|
1059 | 1124 | /* Missing "refclk-type" defaults to external. */ |
---|
1060 | 1125 | fdt_nop_property(initial_boot_params, usbn, "refclk-type"); |
---|