| .. | .. |
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| 106 | 106 | if (section > 3) |
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| 107 | 107 | return -ERANGE; |
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| 108 | 108 | |
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| 109 | | - region->offset = 16 * section; |
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| 109 | + region->offset = 32 * section; |
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| 110 | 110 | region->length = 8; |
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| 111 | 111 | |
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| 112 | 112 | return 0; |
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| .. | .. |
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| 199 | 199 | SPINAND_HAS_QE_BIT, |
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| 200 | 200 | SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout, |
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| 201 | 201 | hyf1gq4udacae_ecc_get_status)), |
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| 202 | + SPINAND_INFO("HYF2GQ4IAACAE", |
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| 203 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x82), |
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| 204 | + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), |
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| 205 | + NAND_ECCREQ(14, 512), |
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| 206 | + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
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| 207 | + &write_cache_variants, |
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| 208 | + &update_cache_variants), |
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| 209 | + SPINAND_HAS_QE_BIT, |
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| 210 | + SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout, |
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| 211 | + hyf1gq4udacae_ecc_get_status)), |
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| 212 | + SPINAND_INFO("HYF1GQ4IDACAE", |
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| 213 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x81), |
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| 214 | + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), |
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| 215 | + NAND_ECCREQ(4, 512), |
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| 216 | + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
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| 217 | + &write_cache_variants, |
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| 218 | + &update_cache_variants), |
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| 219 | + SPINAND_HAS_QE_BIT, |
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| 220 | + SPINAND_ECCINFO(&hyf1gq4udacae_ooblayout, |
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| 221 | + hyf1gq4udacae_ecc_get_status)), |
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| 202 | 222 | }; |
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| 203 | 223 | |
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| 204 | 224 | static const struct spinand_manufacturer_ops hyf_spinand_manuf_ops = { |
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