change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 u-boot/drivers/clk/rockchip/clk_rk3568.c
..
..
@@ -1,7 +1,7 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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  * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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- * Author: Elaine Zhang <zhangqing@rock-chips.com>
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+ * Author: Joseph Chen <chenjh@rock-chips.com>
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  */
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 #include <common.h>
..
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@@ -1160,7 +1160,7 @@
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 	switch (clk_id) {
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 	case CLK_PWM1:
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-		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
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+		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
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 		break;
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 	case CLK_PWM2:
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 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
..
..
@@ -1850,7 +1850,7 @@
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 		rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],
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 				      priv->cru, VPLL, div * rate);
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 	} else {
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-		for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
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+		for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {
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 			switch (i) {
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 			case DCLK_VOP_SEL_GPLL:
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 				pll_rate = priv->gpll_hz;
..
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@@ -3107,9 +3107,15 @@
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 	if (parent->id == PLL_VPLL) {
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 		rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
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 			     DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
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-	} else {
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+	} else if (parent->id == PLL_HPLL) {
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 		rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
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 			     DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
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+	} else if (parent->id == PLL_CPLL) {
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+		rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
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+			     DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT);
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+	} else {
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+		rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
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+			     DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT);
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 	}
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 	return 0;