~hc/RK356X_SDK_RELEASE.git

..	..	@@ -117,6 +117,43 @@
117	117	0:
118	118
119	119	/*
	120	+ * Enable instruction cache (if required), stack pointer,
	121	+ * data access alignment checks and SError.
	122	+ */
	123	+#ifndef CONFIG_SYS_ICACHE_OFF
	124	+ mov x1, #CR_I
	125	+#else
	126	+ mov x1, #0
	127	+#endif
	128	+ switch_el x2, 3f, 2f, 1f
	129	+3: mrs x0, sctlr_el3
	130	+ orr x0, x0, x1
	131	+ msr sctlr_el3, x0
	132	+#ifndef CONFIG_SUPPORT_USBPLUG
	133	+ msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
	134	+#endif
	135	+ b 0f
	136	+2: mrs x0, sctlr_el2
	137	+ orr x0, x0, x1
	138	+ msr sctlr_el2, x0
	139	+
	140	+ mrs x0, hcr_el2
	141	+ orr x0, x0, #HCR_EL2_TGE
	142	+ orr x0, x0, #HCR_EL2_AMO
	143	+#if CONFIG_IS_ENABLED(IRQ)
	144	+ orr x0, x0, #HCR_EL2_IMO
	145	+#endif
	146	+ msr hcr_el2, x0
	147	+ msr daifclr, #4
	148	+ b 0f
	149	+1: mrs x0, sctlr_el1
	150	+ orr x0, x0, x1
	151	+ msr sctlr_el1, x0
	152	+ msr daifclr, #4
	153	+0:
	154	+ isb
	155	+
	156	+ /*
120	157	* Enable SMPEN bit for coherency.
121	158	* This register is not architectural but at the moment
122	159	* this bit should be set for A53/A57/A72.
..	..	@@ -160,6 +197,43 @@
160	197	cbz x0, slave_cpu
161	198	br x0 /* branch to the given address */
162	199	#endif /* CONFIG_ARMV8_MULTIENTRY */
	200	+
	201	+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARM_SMP)
	202	+ mrs x0, mpidr_el1
	203	+ and x0, x0, #0xfff
	204	+ cmp x0, #0
	205	+ beq master_cpu
	206	+
	207	+#ifdef SMP_CPU1
	208	+ cmp x0, #(SMP_CPU1)
	209	+ ldr x1, =(SMP_CPU1_STACK)
	210	+ beq slave_cpu
	211	+#endif
	212	+
	213	+#ifdef SMP_CPU2
	214	+ cmp x0, #(SMP_CPU2)
	215	+ ldr x1, =(SMP_CPU2_STACK)
	216	+ beq slave_cpu
	217	+#endif
	218	+
	219	+#ifdef SMP_CPU3
	220	+ cmp x0, #(SMP_CPU3)
	221	+ ldr x1, =(SMP_CPU3_STACK)
	222	+ beq slave_cpu
	223	+#endif
	224	+ dsb sy
	225	+ isb
	226	+
	227	+loop:
	228	+ wfe
	229	+ b loop
	230	+
	231	+slave_cpu:
	232	+ bic sp, x1, #0xf
	233	+ bl smp_entry
	234	+ b loop
	235	+#endif
	236	+
163	237	master_cpu:
164	238	bl _main
165	239