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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/include/uapi/gpu/arm/bifrost/mali_base_kernel.h
....@@ -1,7 +1,7 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
22 /*
33  *
4
- * (C) COPYRIGHT 2010-2021 ARM Limited. All rights reserved.
4
+ * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
55  *
66  * This program is free software and is provided to you under the terms of the
77  * GNU General Public License version 2 as published by the Free Software
....@@ -27,32 +27,11 @@
2727 #define _UAPI_BASE_KERNEL_H_
2828 
2929 #include <linux/types.h>
30
-
31
-struct base_mem_handle {
32
-	struct {
33
-		__u64 handle;
34
-	} basep;
35
-};
36
-
3730 #include "mali_base_mem_priv.h"
3831 #include "gpu/mali_kbase_gpu_id.h"
3932 #include "gpu/mali_kbase_gpu_coherency.h"
4033 
41
-#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 4
42
-
4334 #define BASE_MAX_COHERENT_GROUPS 16
44
-
45
-#if defined(CDBG_ASSERT)
46
-#define LOCAL_ASSERT CDBG_ASSERT
47
-#elif defined(KBASE_DEBUG_ASSERT)
48
-#define LOCAL_ASSERT KBASE_DEBUG_ASSERT
49
-#else
50
-#if defined(__KERNEL__)
51
-#error assert macro not defined!
52
-#else
53
-#define LOCAL_ASSERT(...)	((void)#__VA_ARGS__)
54
-#endif
55
-#endif
5635 
5736 #if defined(PAGE_MASK) && defined(PAGE_SHIFT)
5837 #define LOCAL_PAGE_SHIFT PAGE_SHIFT
....@@ -162,7 +141,7 @@
162141 #define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES                           \
163142 	(1ull << (BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2))
164143 
165
-/* Bit mask of cookies used for for memory allocation setup */
144
+/* Bit mask of cookies used for memory allocation setup */
166145 #define KBASE_COOKIE_MASK  ~1UL /* bit 0 is reserved */
167146 
168147 /* Maximum size allowed in a single KBASE_IOCTL_MEM_ALLOC call */
....@@ -185,6 +164,12 @@
185164 /**
186165  * struct base_mem_aliasing_info - Memory aliasing info
187166  *
167
+ * @handle: Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
168
+ * @offset: Offset within the handle to start aliasing from, in pages.
169
+ *          Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
170
+ * @length: Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
171
+ *          specifies the number of times the special page is needed.
172
+ *
188173  * Describes a memory handle to be aliased.
189174  * A subset of the handle can be chosen for aliasing, given an offset and a
190175  * length.
....@@ -196,12 +181,6 @@
196181  * Offset and length are specified in pages.
197182  * Offset must be within the size of the handle.
198183  * Offset+length must not overrun the size of the handle.
199
- *
200
- * @handle: Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
201
- * @offset: Offset within the handle to start aliasing from, in pages.
202
- *          Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
203
- * @length: Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
204
- *          specifies the number of times the special page is needed.
205184  */
206185 struct base_mem_aliasing_info {
207186 	struct base_mem_handle handle;
....@@ -217,55 +196,6 @@
217196 /* Maximum number of concurrent just-in-time memory allocations.
218197  */
219198 #define BASE_JIT_ALLOC_COUNT (255)
220
-
221
-/* base_jit_alloc_info in use for kernel driver versions 10.2 to early 11.5
222
- *
223
- * jit_version is 1
224
- *
225
- * Due to the lack of padding specified, user clients between 32 and 64-bit
226
- * may have assumed a different size of the struct
227
- *
228
- * An array of structures was not supported
229
- */
230
-struct base_jit_alloc_info_10_2 {
231
-	__u64 gpu_alloc_addr;
232
-	__u64 va_pages;
233
-	__u64 commit_pages;
234
-	__u64 extension;
235
-	__u8 id;
236
-};
237
-
238
-/* base_jit_alloc_info introduced by kernel driver version 11.5, and in use up
239
- * to 11.19
240
- *
241
- * This structure had a number of modifications during and after kernel driver
242
- * version 11.5, but remains size-compatible throughout its version history, and
243
- * with earlier variants compatible with future variants by requiring
244
- * zero-initialization to the unused space in the structure.
245
- *
246
- * jit_version is 2
247
- *
248
- * Kernel driver version history:
249
- * 11.5: Initial introduction with 'usage_id' and padding[5]. All padding bytes
250
- *       must be zero. Kbase minor version was not incremented, so some
251
- *       versions of 11.5 do not have this change.
252
- * 11.5: Added 'bin_id' and 'max_allocations', replacing 2 padding bytes (Kbase
253
- *       minor version not incremented)
254
- * 11.6: Added 'flags', replacing 1 padding byte
255
- * 11.10: Arrays of this structure are supported
256
- */
257
-struct base_jit_alloc_info_11_5 {
258
-	__u64 gpu_alloc_addr;
259
-	__u64 va_pages;
260
-	__u64 commit_pages;
261
-	__u64 extension;
262
-	__u8 id;
263
-	__u8 bin_id;
264
-	__u8 max_allocations;
265
-	__u8 flags;
266
-	__u8 padding[2];
267
-	__u16 usage_id;
268
-};
269199 
270200 /**
271201  * struct base_jit_alloc_info - Structure which describes a JIT allocation
....@@ -296,16 +226,6 @@
296226  * @heap_info_gpu_addr:         Pointer to an object in GPU memory describing
297227  *                              the actual usage of the region.
298228  *
299
- * jit_version is 3.
300
- *
301
- * When modifications are made to this structure, it is still compatible with
302
- * jit_version 3 when: a) the size is unchanged, and b) new members only
303
- * replace the padding bytes.
304
- *
305
- * Previous jit_version history:
306
- * jit_version == 1, refer to &base_jit_alloc_info_10_2
307
- * jit_version == 2, refer to &base_jit_alloc_info_11_5
308
- *
309229  * Kbase version history:
310230  * 11.20: added @heap_info_gpu_addr
311231  */
....@@ -332,10 +252,9 @@
332252 	__u64 ext_resource;
333253 };
334254 
335
-
336255 /**
337
- * The maximum number of external resources which can be mapped/unmapped
338
- * in a single request.
256
+ * BASE_EXT_RES_COUNT_MAX - The maximum number of external resources
257
+ * which can be mapped/unmapped in a single request.
339258  */
340259 #define BASE_EXT_RES_COUNT_MAX 10
341260 
....@@ -360,7 +279,7 @@
360279 #define GPU_MAX_JOB_SLOTS 16
361280 
362281 /**
363
- * User-side Base GPU Property Queries
282
+ * DOC: User-side Base GPU Property Queries
364283  *
365284  * The User-side Base GPU Property Query interface encapsulates two
366285  * sub-modules:
....@@ -471,51 +390,6 @@
471390  * 16 coherent groups, since core groups are typically 4 cores.
472391  */
473392 
474
-#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 4
475
-
476
-#define BASE_MAX_COHERENT_GROUPS 16
477
-/**
478
- * struct mali_base_gpu_core_props - GPU core props info
479
- * @product_id: Pro specific value.
480
- * @version_status: Status of the GPU release. No defined values, but starts at
481
- * 	0 and increases by one for each release status (alpha, beta, EAC, etc.).
482
- * 	4 bit values (0-15).
483
- * @minor_revision: Minor release number of the GPU. "P" part of an "RnPn"
484
- * 	release number.
485
- * 	8 bit values (0-255).
486
- * @major_revision: Major release number of the GPU. "R" part of an "RnPn"
487
- * 	release number.
488
- * 	4 bit values (0-15).
489
- * @padding: padding to allign to 8-byte
490
- * @gpu_freq_khz_max: The maximum GPU frequency. Reported to applications by
491
- * 	clGetDeviceInfo()
492
- * @log2_program_counter_size: Size of the shader program counter, in bits.
493
- * @texture_features: TEXTURE_FEATURES_x registers, as exposed by the GPU. This
494
- * 	is a bitpattern where a set bit indicates that the format is supported.
495
- * 	Before using a texture format, it is recommended that the corresponding
496
- * 	bit be checked.
497
- * @gpu_available_memory_size: Theoretical maximum memory available to the GPU.
498
- * 	It is unlikely that a client will be able to allocate all of this memory
499
- * 	for their own purposes, but this at least provides an upper bound on the
500
- * 	memory available to the GPU.
501
- * 	This is required for OpenCL's clGetDeviceInfo() call when
502
- * 	CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
503
- * 	client will not be expecting to allocate anywhere near this value.
504
- * @num_exec_engines: The number of execution engines.
505
- */
506
-struct mali_base_gpu_core_props {
507
-	__u32 product_id;
508
-	__u16 version_status;
509
-	__u16 minor_revision;
510
-	__u16 major_revision;
511
-	__u16 padding;
512
-	__u32 gpu_freq_khz_max;
513
-	__u32 log2_program_counter_size;
514
-	__u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
515
-	__u64 gpu_available_memory_size;
516
-	__u8 num_exec_engines;
517
-};
518
-
519393 /*
520394  * More information is possible - but associativity and bus width are not
521395  * required by upper-level apis.
....@@ -546,7 +420,7 @@
546420  *                          field.
547421  * @impl_tech:              0 = Not specified, 1 = Silicon, 2 = FPGA,
548422  *                          3 = SW Model/Emulation
549
- * @padding:                padding to allign to 8-byte
423
+ * @padding:                padding to align to 8-byte
550424  * @tls_alloc:              Number of threads per core that TLS must be
551425  *                          allocated for
552426  */
....@@ -566,16 +440,16 @@
566440  * struct mali_base_gpu_coherent_group - descriptor for a coherent group
567441  * @core_mask: Core restriction mask required for the group
568442  * @num_cores: Number of cores in the group
569
- * @padding:   padding to allign to 8-byte
443
+ * @padding:   padding to align to 8-byte
570444  *
571445  * \c core_mask exposes all cores in that coherent group, and \c num_cores
572
- * 	provides a cached population-count for that mask.
446
+ * provides a cached population-count for that mask.
573447  *
574448  * @note Whilst all cores are exposed in the mask, not all may be available to
575
- * 	the application, depending on the Kernel Power policy.
449
+ *       the application, depending on the Kernel Power policy.
576450  *
577451  * @note if u64s must be 8-byte aligned, then this structure has 32-bits of
578
- * 	wastage.
452
+ *       wastage.
579453  */
580454 struct mali_base_gpu_coherent_group {
581455 	__u64 core_mask;
....@@ -587,15 +461,16 @@
587461  * struct mali_base_gpu_coherent_group_info - Coherency group information
588462  * @num_groups: Number of coherent groups in the GPU.
589463  * @num_core_groups: Number of core groups (coherent or not) in the GPU.
590
- * 	Equivalent to the number of L2 Caches.
591
- * 	  The GPU Counter dumping writes 2048 bytes per core group, regardless
592
- * 	of whether the core groups are coherent or not. Hence this member is
593
- * 	needed to calculate how much memory is required for dumping.
594
- * 	  @note Do not use it to work out how many valid elements are in the
595
- * 	group[] member. Use num_groups instead.
464
+ *                   Equivalent to the number of L2 Caches.
465
+ *                   The GPU Counter dumping writes 2048 bytes per core group,
466
+ *                   regardless of whether the core groups are coherent or not.
467
+ *                   Hence this member is needed to calculate how much memory
468
+ *                   is required for dumping.
469
+ *                   @note Do not use it to work out how many valid elements
470
+ *                         are in the group[] member. Use num_groups instead.
596471  * @coherency: Coherency features of the memory, accessed by gpu_mem_features
597
- * 	methods
598
- * @padding: padding to allign to 8-byte
472
+ *             methods
473
+ * @padding: padding to align to 8-byte
599474  * @group: Descriptors of coherent groups
600475  *
601476  * Note that the sizes of the members could be reduced. However, the \c group
....@@ -612,6 +487,12 @@
612487 	__u32 padding;
613488 	struct mali_base_gpu_coherent_group group[BASE_MAX_COHERENT_GROUPS];
614489 };
490
+
491
+#if MALI_USE_CSF
492
+#include "csf/mali_base_csf_kernel.h"
493
+#else
494
+#include "jm/mali_base_jm_kernel.h"
495
+#endif
615496 
616497 /**
617498  * struct gpu_raw_gpu_props - A complete description of the GPU's Hardware
....@@ -635,7 +516,7 @@
635516  * @thread_max_barrier_size: Maximum number of threads per barrier
636517  * @thread_features: Thread features
637518  * @coherency_mode: Note: This is the _selected_ coherency mode rather than the
638
- * 	available modes as exposed in the coherency_features register
519
+ *                  available modes as exposed in the coherency_features register
639520  * @thread_tls_alloc: Number of threads per core that TLS must be allocated for
640521  * @gpu_features: GPU features
641522  *
....@@ -699,7 +580,7 @@
699580  * values from which the value of the other members are derived. The derived
700581  * members exist to allow for efficient access and/or shielding the details
701582  * of the layout of the registers.
702
- * */
583
+ */
703584 struct base_gpu_props {
704585 	struct mali_base_gpu_core_props core_props;
705586 	struct mali_base_gpu_l2_cache_props l2_props;
....@@ -710,88 +591,24 @@
710591 	struct mali_base_gpu_coherent_group_info coherency_info;
711592 };
712593 
713
-#if MALI_USE_CSF
714
-#include "csf/mali_base_csf_kernel.h"
715
-#else
716
-#include "jm/mali_base_jm_kernel.h"
717
-#endif
594
+#define BASE_MEM_GROUP_ID_GET(flags)                                           \
595
+	((flags & BASE_MEM_GROUP_ID_MASK) >> BASEP_MEM_GROUP_ID_SHIFT)
718596 
719
-/**
720
- * base_mem_group_id_get() - Get group ID from flags
721
- * @flags: Flags to pass to base_mem_alloc
722
- *
723
- * This inline function extracts the encoded group ID from flags
724
- * and converts it into numeric value (0~15).
725
- *
726
- * Return: group ID(0~15) extracted from the parameter
727
- */
728
-static __inline__ int base_mem_group_id_get(base_mem_alloc_flags flags)
729
-{
730
-	LOCAL_ASSERT((flags & ~BASE_MEM_FLAGS_INPUT_MASK) == 0);
731
-	return (int)((flags & BASE_MEM_GROUP_ID_MASK) >>
732
-			BASEP_MEM_GROUP_ID_SHIFT);
733
-}
597
+#define BASE_MEM_GROUP_ID_SET(id)                                              \
598
+	(((base_mem_alloc_flags)((id < 0 || id >= BASE_MEM_GROUP_COUNT) ?      \
599
+					 BASE_MEM_GROUP_DEFAULT :              \
600
+					 id)                                   \
601
+	  << BASEP_MEM_GROUP_ID_SHIFT) &                                       \
602
+	 BASE_MEM_GROUP_ID_MASK)
734603 
735
-/**
736
- * base_mem_group_id_set() - Set group ID into base_mem_alloc_flags
737
- * @id: group ID(0~15) you want to encode
738
- *
739
- * This inline function encodes specific group ID into base_mem_alloc_flags.
740
- * Parameter 'id' should lie in-between 0 to 15.
741
- *
742
- * Return: base_mem_alloc_flags with the group ID (id) encoded
743
- *
744
- * The return value can be combined with other flags against base_mem_alloc
745
- * to identify a specific memory group.
746
- */
747
-static __inline__ base_mem_alloc_flags base_mem_group_id_set(int id)
748
-{
749
-	if ((id < 0) || (id >= BASE_MEM_GROUP_COUNT)) {
750
-		/* Set to default value when id is out of range. */
751
-		id = BASE_MEM_GROUP_DEFAULT;
752
-	}
604
+#define BASE_CONTEXT_MMU_GROUP_ID_SET(group_id)                                \
605
+	(BASEP_CONTEXT_MMU_GROUP_ID_MASK &                                     \
606
+	 ((base_context_create_flags)(group_id)                                \
607
+	  << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT))
753608 
754
-	return ((base_mem_alloc_flags)id << BASEP_MEM_GROUP_ID_SHIFT) &
755
-		BASE_MEM_GROUP_ID_MASK;
756
-}
757
-
758
-/**
759
- * base_context_mmu_group_id_set - Encode a memory group ID in
760
- *                                 base_context_create_flags
761
- *
762
- * Memory allocated for GPU page tables will come from the specified group.
763
- *
764
- * @group_id: Physical memory group ID. Range is 0..(BASE_MEM_GROUP_COUNT-1).
765
- *
766
- * Return: Bitmask of flags to pass to base_context_init.
767
- */
768
-static __inline__ base_context_create_flags base_context_mmu_group_id_set(
769
-	int const group_id)
770
-{
771
-	LOCAL_ASSERT(group_id >= 0);
772
-	LOCAL_ASSERT(group_id < BASE_MEM_GROUP_COUNT);
773
-	return BASEP_CONTEXT_MMU_GROUP_ID_MASK &
774
-		((base_context_create_flags)group_id <<
775
-		BASEP_CONTEXT_MMU_GROUP_ID_SHIFT);
776
-}
777
-
778
-/**
779
- * base_context_mmu_group_id_get - Decode a memory group ID from
780
- *                                 base_context_create_flags
781
- *
782
- * Memory allocated for GPU page tables will come from the returned group.
783
- *
784
- * @flags: Bitmask of flags to pass to base_context_init.
785
- *
786
- * Return: Physical memory group ID. Valid range is 0..(BASE_MEM_GROUP_COUNT-1).
787
- */
788
-static __inline__ int base_context_mmu_group_id_get(
789
-	base_context_create_flags const flags)
790
-{
791
-	LOCAL_ASSERT(flags == (flags & BASEP_CONTEXT_CREATE_ALLOWED_FLAGS));
792
-	return (int)((flags & BASEP_CONTEXT_MMU_GROUP_ID_MASK) >>
793
-			BASEP_CONTEXT_MMU_GROUP_ID_SHIFT);
794
-}
609
+#define BASE_CONTEXT_MMU_GROUP_ID_GET(flags)                                   \
610
+	((flags & BASEP_CONTEXT_MMU_GROUP_ID_MASK) >>                          \
611
+	 BASEP_CONTEXT_MMU_GROUP_ID_SHIFT)
795612 
796613 /*
797614  * A number of bit flags are defined for requesting cpu_gpu_timeinfo. These