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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_jm.h
....@@ -1,7 +1,7 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
22 /*
33  *
4
- * (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
4
+ * (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
55  *
66  * This program is free software and is provided to you under the terms of the
77  * GNU General Public License version 2 as published by the Free Software
....@@ -22,114 +22,11 @@
2222 #ifndef _UAPI_KBASE_GPU_REGMAP_JM_H_
2323 #define _UAPI_KBASE_GPU_REGMAP_JM_H_
2424 
25
-#if MALI_USE_CSF && defined(__KERNEL__)
26
-#error "Cannot be compiled with CSF"
27
-#endif
28
-
29
-/* Set to implementation defined, outer caching */
30
-#define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull
31
-/* Set to write back memory, outer caching */
32
-#define AS_MEMATTR_AARCH64_OUTER_WA       0x8Dull
33
-/* Set to inner non-cacheable, outer-non-cacheable
34
- * Setting defined by the alloc bits is ignored, but set to a valid encoding:
35
- * - no-alloc on read
36
- * - no alloc on write
37
- */
38
-#define AS_MEMATTR_AARCH64_NON_CACHEABLE  0x4Cull
39
-
40
-/* Symbols for default MEMATTR to use
41
- * Default is - HW implementation defined caching
42
- */
43
-#define AS_MEMATTR_INDEX_DEFAULT               0
44
-#define AS_MEMATTR_INDEX_DEFAULT_ACE           3
45
-
46
-/* HW implementation defined caching */
47
-#define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0
48
-/* Force cache on */
49
-#define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL    1
50
-/* Write-alloc */
51
-#define AS_MEMATTR_INDEX_WRITE_ALLOC           2
52
-/* Outer coherent, inner implementation defined policy */
53
-#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF        3
54
-/* Outer coherent, write alloc inner */
55
-#define AS_MEMATTR_INDEX_OUTER_WA              4
56
-/* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */
57
-#define AS_MEMATTR_INDEX_NON_CACHEABLE         5
58
-
5925 /* GPU control registers */
6026 
61
-#define CORE_FEATURES           0x008   /* (RO) Shader Core Features */
62
-#define JS_PRESENT              0x01C   /* (RO) Job slots present */
63
-#define LATEST_FLUSH            0x038   /* (RO) Flush ID of latest
64
-					 * clean-and-invalidate operation
65
-					 */
66
-
67
-#define PRFCNT_BASE_LO   0x060  /* (RW) Performance counter memory
68
-				 * region base address, low word
69
-				 */
70
-#define PRFCNT_BASE_HI   0x064  /* (RW) Performance counter memory
71
-				 * region base address, high word
72
-				 */
73
-#define PRFCNT_CONFIG    0x068  /* (RW) Performance counter
74
-				 * configuration
75
-				 */
76
-#define PRFCNT_JM_EN     0x06C  /* (RW) Performance counter enable
77
-				 * flags for Job Manager
78
-				 */
79
-#define PRFCNT_SHADER_EN 0x070  /* (RW) Performance counter enable
80
-				 * flags for shader cores
81
-				 */
82
-#define PRFCNT_TILER_EN  0x074  /* (RW) Performance counter enable
83
-				 * flags for tiler
84
-				 */
85
-#define PRFCNT_MMU_L2_EN 0x07C  /* (RW) Performance counter enable
86
-				 * flags for MMU/L2 cache
87
-				 */
88
-
89
-#define JS0_FEATURES            0x0C0   /* (RO) Features of job slot 0 */
90
-#define JS1_FEATURES            0x0C4   /* (RO) Features of job slot 1 */
91
-#define JS2_FEATURES            0x0C8   /* (RO) Features of job slot 2 */
92
-#define JS3_FEATURES            0x0CC   /* (RO) Features of job slot 3 */
93
-#define JS4_FEATURES            0x0D0   /* (RO) Features of job slot 4 */
94
-#define JS5_FEATURES            0x0D4   /* (RO) Features of job slot 5 */
95
-#define JS6_FEATURES            0x0D8   /* (RO) Features of job slot 6 */
96
-#define JS7_FEATURES            0x0DC   /* (RO) Features of job slot 7 */
97
-#define JS8_FEATURES            0x0E0   /* (RO) Features of job slot 8 */
98
-#define JS9_FEATURES            0x0E4   /* (RO) Features of job slot 9 */
99
-#define JS10_FEATURES           0x0E8   /* (RO) Features of job slot 10 */
100
-#define JS11_FEATURES           0x0EC   /* (RO) Features of job slot 11 */
101
-#define JS12_FEATURES           0x0F0   /* (RO) Features of job slot 12 */
102
-#define JS13_FEATURES           0x0F4   /* (RO) Features of job slot 13 */
103
-#define JS14_FEATURES           0x0F8   /* (RO) Features of job slot 14 */
104
-#define JS15_FEATURES           0x0FC   /* (RO) Features of job slot 15 */
105
-
106
-#define JS_FEATURES_REG(n)      GPU_CONTROL_REG(JS0_FEATURES + ((n) << 2))
107
-
108
-#define JM_CONFIG               0xF00   /* (RW) Job manager configuration (implementation-specific) */
27
+#define LATEST_FLUSH           0x038 /* (RO) Flush ID of latest clean-and-invalidate operation */
10928 
11029 /* Job control registers */
111
-
112
-#define JOB_IRQ_JS_STATE        0x010   /* status==active and _next == busy snapshot from last JOB_IRQ_CLEAR */
113
-#define JOB_IRQ_THROTTLE        0x014   /* cycles to delay delivering an interrupt externally. The JOB_IRQ_STATUS is NOT affected by this, just the delivery of the interrupt.  */
114
-
115
-#define JOB_SLOT0               0x800   /* Configuration registers for job slot 0 */
116
-#define JOB_SLOT1               0x880   /* Configuration registers for job slot 1 */
117
-#define JOB_SLOT2               0x900   /* Configuration registers for job slot 2 */
118
-#define JOB_SLOT3               0x980   /* Configuration registers for job slot 3 */
119
-#define JOB_SLOT4               0xA00   /* Configuration registers for job slot 4 */
120
-#define JOB_SLOT5               0xA80   /* Configuration registers for job slot 5 */
121
-#define JOB_SLOT6               0xB00   /* Configuration registers for job slot 6 */
122
-#define JOB_SLOT7               0xB80   /* Configuration registers for job slot 7 */
123
-#define JOB_SLOT8               0xC00   /* Configuration registers for job slot 8 */
124
-#define JOB_SLOT9               0xC80   /* Configuration registers for job slot 9 */
125
-#define JOB_SLOT10              0xD00   /* Configuration registers for job slot 10 */
126
-#define JOB_SLOT11              0xD80   /* Configuration registers for job slot 11 */
127
-#define JOB_SLOT12              0xE00   /* Configuration registers for job slot 12 */
128
-#define JOB_SLOT13              0xE80   /* Configuration registers for job slot 13 */
129
-#define JOB_SLOT14              0xF00   /* Configuration registers for job slot 14 */
130
-#define JOB_SLOT15              0xF80   /* Configuration registers for job slot 15 */
131
-
132
-#define JOB_SLOT_REG(n, r)      (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r))
13330 
13431 #define JS_HEAD_LO             0x00	/* (RO) Job queue head pointer for job slot n, low word */
13532 #define JS_HEAD_HI             0x04	/* (RO) Job queue head pointer for job slot n, high word */
....@@ -138,150 +35,16 @@
13835 #define JS_AFFINITY_LO         0x10	/* (RO) Core affinity mask for job slot n, low word */
13936 #define JS_AFFINITY_HI         0x14	/* (RO) Core affinity mask for job slot n, high word */
14037 #define JS_CONFIG              0x18	/* (RO) Configuration settings for job slot n */
141
-/* (RO) Extended affinity mask for job slot n*/
142
-#define JS_XAFFINITY           0x1C
143
-
144
-#define JS_COMMAND             0x20	/* (WO) Command register for job slot n */
145
-#define JS_STATUS              0x24	/* (RO) Status register for job slot n */
14638 
14739 #define JS_HEAD_NEXT_LO        0x40	/* (RW) Next job queue head pointer for job slot n, low word */
14840 #define JS_HEAD_NEXT_HI        0x44	/* (RW) Next job queue head pointer for job slot n, high word */
149
-
15041 #define JS_AFFINITY_NEXT_LO    0x50	/* (RW) Next core affinity mask for job slot n, low word */
15142 #define JS_AFFINITY_NEXT_HI    0x54	/* (RW) Next core affinity mask for job slot n, high word */
15243 #define JS_CONFIG_NEXT         0x58	/* (RW) Next configuration settings for job slot n */
153
-/* (RW) Next extended affinity mask for job slot n */
154
-#define JS_XAFFINITY_NEXT      0x5C
155
-
15644 #define JS_COMMAND_NEXT        0x60	/* (RW) Next command register for job slot n */
15745 
158
-#define JS_FLUSH_ID_NEXT       0x70	/* (RW) Next job slot n cache flush ID */
46
+#define JOB_SLOT0               0x800   /* Configuration registers for job slot 0 */
15947 
160
-/* No JM-specific MMU control registers */
161
-/* No JM-specific MMU address space control registers */
162
-
163
-/* JS_COMMAND register commands */
164
-#define JS_COMMAND_NOP         0x00	/* NOP Operation. Writing this value is ignored */
165
-#define JS_COMMAND_START       0x01	/* Start processing a job chain. Writing this value is ignored */
166
-#define JS_COMMAND_SOFT_STOP   0x02	/* Gently stop processing a job chain */
167
-#define JS_COMMAND_HARD_STOP   0x03	/* Rudely stop processing a job chain */
168
-#define JS_COMMAND_SOFT_STOP_0 0x04	/* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
169
-#define JS_COMMAND_HARD_STOP_0 0x05	/* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
170
-#define JS_COMMAND_SOFT_STOP_1 0x06	/* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
171
-#define JS_COMMAND_HARD_STOP_1 0x07	/* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
172
-
173
-#define JS_COMMAND_MASK        0x07    /* Mask of bits currently in use by the HW */
174
-
175
-/* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
176
-#define JS_CONFIG_START_FLUSH_NO_ACTION        (0u << 0)
177
-#define JS_CONFIG_START_FLUSH_CLEAN            (1u << 8)
178
-#define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8)
179
-#define JS_CONFIG_START_MMU                    (1u << 10)
180
-#define JS_CONFIG_JOB_CHAIN_FLAG               (1u << 11)
181
-#define JS_CONFIG_END_FLUSH_NO_ACTION          JS_CONFIG_START_FLUSH_NO_ACTION
182
-#define JS_CONFIG_END_FLUSH_CLEAN              (1u << 12)
183
-#define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE   (3u << 12)
184
-#define JS_CONFIG_ENABLE_FLUSH_REDUCTION       (1u << 14)
185
-#define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK     (1u << 15)
186
-#define JS_CONFIG_THREAD_PRI(n)                ((n) << 16)
187
-
188
-/* JS_XAFFINITY register values */
189
-#define JS_XAFFINITY_XAFFINITY_ENABLE (1u << 0)
190
-#define JS_XAFFINITY_TILER_ENABLE     (1u << 8)
191
-#define JS_XAFFINITY_CACHE_ENABLE     (1u << 16)
192
-
193
-/* JS_STATUS register values */
194
-
195
-/* NOTE: Please keep this values in sync with enum base_jd_event_code in mali_base_kernel.h.
196
- * The values are separated to avoid dependency of userspace and kernel code.
197
- */
198
-
199
-/* Group of values representing the job status instead of a particular fault */
200
-#define JS_STATUS_NO_EXCEPTION_BASE   0x00
201
-#define JS_STATUS_INTERRUPTED         (JS_STATUS_NO_EXCEPTION_BASE + 0x02)	/* 0x02 means INTERRUPTED */
202
-#define JS_STATUS_STOPPED             (JS_STATUS_NO_EXCEPTION_BASE + 0x03)	/* 0x03 means STOPPED */
203
-#define JS_STATUS_TERMINATED          (JS_STATUS_NO_EXCEPTION_BASE + 0x04)	/* 0x04 means TERMINATED */
204
-
205
-/* General fault values */
206
-#define JS_STATUS_FAULT_BASE          0x40
207
-#define JS_STATUS_CONFIG_FAULT        (JS_STATUS_FAULT_BASE)	/* 0x40 means CONFIG FAULT */
208
-#define JS_STATUS_POWER_FAULT         (JS_STATUS_FAULT_BASE + 0x01)	/* 0x41 means POWER FAULT */
209
-#define JS_STATUS_READ_FAULT          (JS_STATUS_FAULT_BASE + 0x02)	/* 0x42 means READ FAULT */
210
-#define JS_STATUS_WRITE_FAULT         (JS_STATUS_FAULT_BASE + 0x03)	/* 0x43 means WRITE FAULT */
211
-#define JS_STATUS_AFFINITY_FAULT      (JS_STATUS_FAULT_BASE + 0x04)	/* 0x44 means AFFINITY FAULT */
212
-#define JS_STATUS_BUS_FAULT           (JS_STATUS_FAULT_BASE + 0x08)	/* 0x48 means BUS FAULT */
213
-
214
-/* Instruction or data faults */
215
-#define JS_STATUS_INSTRUCTION_FAULT_BASE  0x50
216
-#define JS_STATUS_INSTR_INVALID_PC        (JS_STATUS_INSTRUCTION_FAULT_BASE)	/* 0x50 means INSTR INVALID PC */
217
-#define JS_STATUS_INSTR_INVALID_ENC       (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x01)	/* 0x51 means INSTR INVALID ENC */
218
-#define JS_STATUS_INSTR_TYPE_MISMATCH     (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x02)	/* 0x52 means INSTR TYPE MISMATCH */
219
-#define JS_STATUS_INSTR_OPERAND_FAULT     (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x03)	/* 0x53 means INSTR OPERAND FAULT */
220
-#define JS_STATUS_INSTR_TLS_FAULT         (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x04)	/* 0x54 means INSTR TLS FAULT */
221
-#define JS_STATUS_INSTR_BARRIER_FAULT     (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x05)	/* 0x55 means INSTR BARRIER FAULT */
222
-#define JS_STATUS_INSTR_ALIGN_FAULT       (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x06)	/* 0x56 means INSTR ALIGN FAULT */
223
-/* NOTE: No fault with 0x57 code defined in spec. */
224
-#define JS_STATUS_DATA_INVALID_FAULT      (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x08)	/* 0x58 means DATA INVALID FAULT */
225
-#define JS_STATUS_TILE_RANGE_FAULT        (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x09)	/* 0x59 means TILE RANGE FAULT */
226
-#define JS_STATUS_ADDRESS_RANGE_FAULT     (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x0A)	/* 0x5A means ADDRESS RANGE FAULT */
227
-
228
-/* Other faults */
229
-#define JS_STATUS_MEMORY_FAULT_BASE   0x60
230
-#define JS_STATUS_OUT_OF_MEMORY       (JS_STATUS_MEMORY_FAULT_BASE)	/* 0x60 means OUT OF MEMORY */
231
-#define JS_STATUS_UNKNOWN             0x7F	/* 0x7F means UNKNOWN */
232
-
233
-/* JS<n>_FEATURES register */
234
-#define JS_FEATURE_NULL_JOB              (1u << 1)
235
-#define JS_FEATURE_SET_VALUE_JOB         (1u << 2)
236
-#define JS_FEATURE_CACHE_FLUSH_JOB       (1u << 3)
237
-#define JS_FEATURE_COMPUTE_JOB           (1u << 4)
238
-#define JS_FEATURE_VERTEX_JOB            (1u << 5)
239
-#define JS_FEATURE_GEOMETRY_JOB          (1u << 6)
240
-#define JS_FEATURE_TILER_JOB             (1u << 7)
241
-#define JS_FEATURE_FUSED_JOB             (1u << 8)
242
-#define JS_FEATURE_FRAGMENT_JOB          (1u << 9)
243
-
244
-/* JM_CONFIG register */
245
-#define JM_TIMESTAMP_OVERRIDE  (1ul << 0)
246
-#define JM_CLOCK_GATE_OVERRIDE (1ul << 1)
247
-#define JM_JOB_THROTTLE_ENABLE (1ul << 2)
248
-#define JM_JOB_THROTTLE_LIMIT_SHIFT (3)
249
-#define JM_MAX_JOB_THROTTLE_LIMIT (0x3F)
250
-#define JM_FORCE_COHERENCY_FEATURES_SHIFT (2)
251
-
252
-/* GPU_COMMAND values */
253
-#define GPU_COMMAND_NOP                0x00 /* No operation, nothing happens */
254
-#define GPU_COMMAND_SOFT_RESET         0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */
255
-#define GPU_COMMAND_HARD_RESET         0x02 /* Immediately reset the entire GPU. */
256
-#define GPU_COMMAND_PRFCNT_CLEAR       0x03 /* Clear all performance counters, setting them all to zero. */
257
-#define GPU_COMMAND_PRFCNT_SAMPLE      0x04 /* Sample all performance counters, writing them out to memory */
258
-#define GPU_COMMAND_CYCLE_COUNT_START  0x05 /* Starts the cycle counter, and system timestamp propagation */
259
-#define GPU_COMMAND_CYCLE_COUNT_STOP   0x06 /* Stops the cycle counter, and system timestamp propagation */
260
-#define GPU_COMMAND_CLEAN_CACHES       0x07 /* Clean all caches */
261
-#define GPU_COMMAND_CLEAN_INV_CACHES   0x08 /* Clean and invalidate all caches */
262
-#define GPU_COMMAND_SET_PROTECTED_MODE 0x09 /* Places the GPU in protected mode */
263
-
264
-/* IRQ flags */
265
-#define GPU_FAULT               (1 << 0)    /* A GPU Fault has occurred */
266
-#define MULTIPLE_GPU_FAULTS     (1 << 7)    /* More than one GPU Fault occurred.  */
267
-#define RESET_COMPLETED         (1 << 8)    /* Set when a reset has completed.  */
268
-#define POWER_CHANGED_SINGLE    (1 << 9)    /* Set when a single core has finished powering up or down. */
269
-#define POWER_CHANGED_ALL       (1 << 10)   /* Set when all cores have finished powering up or down. */
270
-#define PRFCNT_SAMPLE_COMPLETED (1 << 16)   /* Set when a performance count sample has completed. */
271
-#define CLEAN_CACHES_COMPLETED  (1 << 17)   /* Set when a cache clean operation has completed. */
272
-
273
-/*
274
- * In Debug build,
275
- * GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and enable interupts sources of GPU_IRQ
276
- * by writing it onto GPU_IRQ_CLEAR/MASK registers.
277
- *
278
- * In Release build,
279
- * GPU_IRQ_REG_COMMON is used.
280
- *
281
- * Note:
282
- * CLEAN_CACHES_COMPLETED - Used separately for cache operation.
283
- */
284
-#define GPU_IRQ_REG_COMMON (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \
285
-		| POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED)
48
+#define JOB_SLOT_REG(n, r)      (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r))
28649 
28750 #endif /* _UAPI_KBASE_GPU_REGMAP_JM_H_ */