change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/tty/serial/8250/8250_fintek.c
..
..
@@ -19,6 +19,7 @@
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 #define CHIP_ID2  0x21
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 #define CHIP_ID_F81865 0x0407
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 #define CHIP_ID_F81866 0x1010
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+#define CHIP_ID_F81966 0x0215
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 #define CHIP_ID_F81216AD 0x1602
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 #define CHIP_ID_F81216H 0x0501
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 #define CHIP_ID_F81216 0x0802
..
..
@@ -62,9 +63,9 @@
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 #define F81216_LDN_HIGH	0x4
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64
 
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 /*
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- * F81866 registers
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+ * F81866/966 registers
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  *
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- * The IRQ setting mode of F81866 is not the same with F81216 series.
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+ * The IRQ setting mode of F81866/966 is not the same with F81216 series.
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  *	Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
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  *	Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
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  *
..
..
@@ -155,6 +156,7 @@
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 	switch (chip) {
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 	case CHIP_ID_F81865:
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 	case CHIP_ID_F81866:
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81216AD:
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 	case CHIP_ID_F81216H:
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 	case CHIP_ID_F81216:
..
..
@@ -171,6 +173,7 @@
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 				     int *max)
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 {
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 	switch (pdata->pid) {
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81865:
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 	case CHIP_ID_F81866:
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 		*min = F81866_LDN_LOW;
..
..
@@ -197,12 +200,12 @@
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 	if (!pdata)
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 		return -EINVAL;
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-	/* Hardware do not support same RTS level on send and receive */
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-	if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
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-			!(rs485->flags & SER_RS485_RTS_AFTER_SEND))
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-		return -EINVAL;
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 	if (rs485->flags & SER_RS485_ENABLED) {
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+		/* Hardware do not support same RTS level on send and receive */
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+		if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
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+		    !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
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+			return -EINVAL;
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 		memset(rs485->padding, 0, sizeof(rs485->padding));
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 		config |= RS485_URA;
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 	} else {
..
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@@ -248,10 +251,11 @@
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 	sio_write_reg(pdata, LDN, pdata->index);
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 	switch (pdata->pid) {
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81866:
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 		sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
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 				   0);
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-		/* fall through */
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+		fallthrough;
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 	case CHIP_ID_F81865:
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 		sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
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 				   F81866_IRQ_SHARE);
..
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@@ -274,6 +278,7 @@
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 {
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 	switch (pdata->pid) {
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 	case CHIP_ID_F81216H: /* 128Bytes FIFO */
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81866:
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 		sio_write_mask_reg(pdata, FIFO_CTRL,
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 				   FIFO_MODE_MASK | RXFTHR_MODE_MASK,
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..
@@ -285,26 +290,9 @@
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 	}
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 }
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292
 
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-static void fintek_8250_goto_highspeed(struct uart_8250_port *uart,
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-			      struct fintek_8250 *pdata)
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-{
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-	sio_write_reg(pdata, LDN, pdata->index);
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-
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-	switch (pdata->pid) {
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-	case CHIP_ID_F81866: /* set uart clock for high speed serial mode */
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-		sio_write_mask_reg(pdata, F81866_UART_CLK,
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-			F81866_UART_CLK_MASK,
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-			F81866_UART_CLK_14_769MHZ);
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-
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-		uart->port.uartclk = 921600 * 16;
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-		break;
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-	default: /* leave clock speed untouched */
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-		break;
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-	}
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-}
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-
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-void fintek_8250_set_termios(struct uart_port *port, struct ktermios *termios,
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-			struct ktermios *old)
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+static void fintek_8250_set_termios(struct uart_port *port,
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+				    struct ktermios *termios,
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+				    struct ktermios *old)
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 {
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 	struct fintek_8250 *pdata = port->private_data;
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 	unsigned int baud = tty_termios_baud_rate(termios);
..
..
@@ -326,6 +314,7 @@
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 	case CHIP_ID_F81216H:
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 		reg = RS485;
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 		break;
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81866:
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 		reg = F81866_UART_CLK;
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 		break;
..
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@@ -372,6 +361,7 @@
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 	switch (pdata->pid) {
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 	case CHIP_ID_F81216H:
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81866:
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 		uart->port.set_termios = fintek_8250_set_termios;
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 		break;
..
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@@ -421,7 +411,6 @@
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 				fintek_8250_set_irq_mode(pdata, level_mode);
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 				fintek_8250_set_max_fifo(pdata);
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-				fintek_8250_goto_highspeed(uart, pdata);
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 				fintek_8250_exit_key(addr[i]);
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..
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@@ -442,6 +431,7 @@
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 	switch (pdata->pid) {
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 	case CHIP_ID_F81216AD:
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 	case CHIP_ID_F81216H:
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+	case CHIP_ID_F81966:
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 	case CHIP_ID_F81866:
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 	case CHIP_ID_F81865:
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 		uart->port.rs485_config = fintek_8250_rs485_config;