~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8	#include <linux/delay.h>
9	9	#include <linux/interrupt.h>
10	10	#include <linux/module.h>
	11	+#include <linux/nvmem-consumer.h>
11	12	#include <linux/of.h>
12	13	#include <linux/of_gpio.h>
13	14	#include <linux/of_graph.h>
..	..	@@ -17,14 +18,16 @@
17	18	#include <linux/pm_runtime.h>
18	19	#include <linux/pinctrl/consumer.h>
19	20	#include <linux/regmap.h>
	21	+#include <media/videobuf2-cma-sg.h>
20	22	#include <media/videobuf2-dma-contig.h>
	23	+#include <media/videobuf2-dma-sg.h>
21	24	#include <media/v4l2-fwnode.h>
22	25	#include <linux/iommu.h>
23		-#include <dt-bindings/soc/rockchip-system-status.h>
24	26	#include <soc/rockchip/rockchip-system-status.h>
25	27	#include <linux/io.h>
26	28	#include <linux/mfd/syscon.h>
27		-#include "dev.h"
	29	+#include <soc/rockchip/rockchip_iommu.h>
	30	+#include "common.h"
28	31
29	32	static const struct cif_reg px30_cif_regs[] = {
30	33	[CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
..	..	@@ -597,6 +600,377 @@
597	600	[CIF_REG_GRF_CIFIO_CON1] = CIF_REG(CIF_GRF_VI_CON1),
598	601	};
599	602
	603	+static const char * const rk3588_cif_clks[] = {
	604	+ "aclk_cif",
	605	+ "hclk_cif",
	606	+ "dclk_cif",
	607	+ "iclk_host0",
	608	+ "iclk_host1",
	609	+};
	610	+
	611	+static const char * const rk3588_cif_rsts[] = {
	612	+ "rst_cif_a",
	613	+ "rst_cif_h",
	614	+ "rst_cif_d",
	615	+ "rst_cif_host0",
	616	+ "rst_cif_host1",
	617	+ "rst_cif_host2",
	618	+ "rst_cif_host3",
	619	+ "rst_cif_host4",
	620	+ "rst_cif_host5",
	621	+};
	622	+
	623	+static const struct cif_reg rk3588_cif_regs[] = {
	624	+ [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
	625	+ [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
	626	+ [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
	627	+ [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
	628	+ [CIF_REG_DVP_MULTI_ID] = CIF_REG(DVP_MULTI_ID),
	629	+ [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
	630	+ [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
	631	+ [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
	632	+ [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
	633	+ [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
	634	+ [CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(DVP_FRM0_ADDR_Y_ID1),
	635	+ [CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(DVP_FRM0_ADDR_UV_ID1),
	636	+ [CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(DVP_FRM1_ADDR_Y_ID1),
	637	+ [CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(DVP_FRM1_ADDR_UV_ID1),
	638	+ [CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(DVP_FRM0_ADDR_Y_ID2),
	639	+ [CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(DVP_FRM0_ADDR_UV_ID2),
	640	+ [CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(DVP_FRM1_ADDR_Y_ID2),
	641	+ [CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(DVP_FRM1_ADDR_UV_ID2),
	642	+ [CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(DVP_FRM0_ADDR_Y_ID3),
	643	+ [CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(DVP_FRM0_ADDR_UV_ID3),
	644	+ [CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(DVP_FRM1_ADDR_Y_ID3),
	645	+ [CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(DVP_FRM1_ADDR_UV_ID3),
	646	+ [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
	647	+ [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
	648	+ [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
	649	+ [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
	650	+ [CIF_REG_DVP_LINE_INT_NUM1] = CIF_REG(DVP_LINE_INT_NUM_23),
	651	+ [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_INT_NUM_01),
	652	+ [CIF_REG_DVP_LINE_CNT1] = CIF_REG(DVP_LINE_INT_NUM_23),
	653	+
	654	+ [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
	655	+ [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
	656	+ [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
	657	+ [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
	658	+ [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
	659	+ [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
	660	+ [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
	661	+ [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
	662	+ [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
	663	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
	664	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
	665	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
	666	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
	667	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
	668	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
	669	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
	670	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
	671	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
	672	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
	673	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
	674	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
	675	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
	676	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
	677	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
	678	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
	679	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
	680	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
	681	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
	682	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
	683	+ [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
	684	+ [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
	685	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
	686	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
	687	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
	688	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
	689	+ [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
	690	+ [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
	691	+ [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
	692	+ [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
	693	+ [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
	694	+ [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
	695	+ [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
	696	+ [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
	697	+ [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
	698	+ [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
	699	+ [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
	700	+ [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
	701	+ [CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0),
	702	+ [CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1),
	703	+ [CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2),
	704	+ [CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3),
	705	+ [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
	706	+
	707	+ [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
	708	+ [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
	709	+ [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
	710	+
	711	+ [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
	712	+ [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
	713	+ [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
	714	+ [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
	715	+ [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
	716	+ [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
	717	+ [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
	718	+ [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
	719	+ [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
	720	+ [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
	721	+ [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
	722	+ [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
	723	+ [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
	724	+ [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
	725	+ [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
	726	+ [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
	727	+ [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
	728	+ [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
	729	+ [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
	730	+ [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
	731	+ [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
	732	+ [CIF_REG_TOISP1_CTRL] = CIF_REG(TOISP1_CH_CTRL),
	733	+ [CIF_REG_TOISP1_SIZE] = CIF_REG(TOISP1_CROP_SIZE),
	734	+ [CIF_REG_TOISP1_CROP] = CIF_REG(TOISP1_CROP),
	735	+ [CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_SOC_CON2),
	736	+};
	737	+
	738	+static const char * const rv1106_cif_clks[] = {
	739	+ "aclk_cif",
	740	+ "hclk_cif",
	741	+ "dclk_cif",
	742	+ "pclk_cif",
	743	+ "i0clk_cif",
	744	+ "i1clk_cif",
	745	+ "rx0clk_cif",
	746	+ "rx1clk_cif",
	747	+ "isp0clk_cif",
	748	+ "sclk_m0_cif",
	749	+ "sclk_m1_cif",
	750	+ "pclk_vepu_cif",
	751	+};
	752	+
	753	+static const char * const rv1106_cif_rsts[] = {
	754	+ "rst_cif_a",
	755	+ "rst_cif_h",
	756	+ "rst_cif_d",
	757	+ "rst_cif_p",
	758	+ "rst_cif_i0",
	759	+ "rst_cif_i1",
	760	+ "rst_cif_rx0",
	761	+ "rst_cif_rx1",
	762	+ "rst_cif_isp0",
	763	+ "rst_cif_pclk_vepu",
	764	+};
	765	+
	766	+static const struct cif_reg rv1106_cif_regs[] = {
	767	+ [CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
	768	+ [CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
	769	+ [CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
	770	+ [CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
	771	+ [CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
	772	+ [CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
	773	+ [CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
	774	+ [CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
	775	+ [CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
	776	+ [CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
	777	+ [CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
	778	+ [CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
	779	+ [CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
	780	+ [CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_CNT_01),
	781	+
	782	+ [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
	783	+ [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
	784	+ [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
	785	+ [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
	786	+ [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
	787	+ [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
	788	+ [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
	789	+ [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
	790	+ [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
	791	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
	792	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
	793	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
	794	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
	795	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
	796	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
	797	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
	798	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
	799	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
	800	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
	801	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
	802	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
	803	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
	804	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
	805	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
	806	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
	807	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
	808	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
	809	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
	810	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
	811	+ [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
	812	+ [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
	813	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
	814	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
	815	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
	816	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
	817	+ [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
	818	+ [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
	819	+ [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
	820	+ [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
	821	+ [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
	822	+ [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
	823	+ [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
	824	+ [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
	825	+ [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
	826	+ [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
	827	+ [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
	828	+ [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
	829	+ [CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0),
	830	+ [CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1),
	831	+ [CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2),
	832	+ [CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3),
	833	+ [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
	834	+ [CIF_REG_LVDS_ID0_CTRL0] = CIF_REG(CIF_LVDS0_ID0_CTRL0),
	835	+ [CIF_REG_LVDS_ID1_CTRL0] = CIF_REG(CIF_LVDS0_ID1_CTRL0),
	836	+ [CIF_REG_LVDS_ID2_CTRL0] = CIF_REG(CIF_LVDS0_ID2_CTRL0),
	837	+ [CIF_REG_LVDS_ID3_CTRL0] = CIF_REG(CIF_LVDS0_ID3_CTRL0),
	838	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106),
	839	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106),
	840	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106),
	841	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106),
	842	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106),
	843	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106),
	844	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106),
	845	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106),
	846	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106),
	847	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106),
	848	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106),
	849	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106),
	850	+ [CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106),
	851	+ [CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106),
	852	+ [CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106),
	853	+ [CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106),
	854	+ [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
	855	+ [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
	856	+ [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
	857	+
	858	+ [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
	859	+ [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
	860	+ [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
	861	+ [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
	862	+ [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
	863	+ [CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
	864	+ [CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
	865	+ [CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
	866	+ [CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
	867	+ [CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
	868	+ [CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
	869	+ [CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
	870	+ [CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
	871	+ [CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
	872	+ [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
	873	+ [CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
	874	+ [CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
	875	+ [CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
	876	+
	877	+ [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
	878	+ [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
	879	+ [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
	880	+ [CIF_REG_GRF_CIFIO_CON] = CIF_REG(RV1106_CIF_GRF_VI_CON),
	881	+ [CIF_REG_GRF_CIFIO_VENC] = CIF_REG(RV1106_CIF_GRF_VENC_WRAPPER),
	882	+};
	883	+
	884	+static const char * const rk3562_cif_clks[] = {
	885	+ "aclk_cif",
	886	+ "hclk_cif",
	887	+ "dclk_cif",
	888	+ "csirx0_data",
	889	+ "csirx1_data",
	890	+ "csirx2_data",
	891	+ "csirx3_data",
	892	+};
	893	+
	894	+static const char * const rk3562_cif_rsts[] = {
	895	+ "rst_cif_a",
	896	+ "rst_cif_h",
	897	+ "rst_cif_d",
	898	+ "rst_cif_i0",
	899	+ "rst_cif_i1",
	900	+ "rst_cif_i2",
	901	+ "rst_cif_i3",
	902	+};
	903	+
	904	+static const struct cif_reg rk3562_cif_regs[] = {
	905	+ [CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
	906	+ [CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
	907	+ [CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
	908	+ [CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
	909	+ [CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
	910	+ [CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
	911	+ [CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
	912	+ [CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
	913	+ [CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
	914	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
	915	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
	916	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
	917	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
	918	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
	919	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
	920	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
	921	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
	922	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
	923	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
	924	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
	925	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
	926	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
	927	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
	928	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
	929	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
	930	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
	931	+ [CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
	932	+ [CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
	933	+ [CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
	934	+ [CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
	935	+ [CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
	936	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
	937	+ [CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
	938	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
	939	+ [CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
	940	+ [CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
	941	+ [CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
	942	+ [CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
	943	+ [CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
	944	+ [CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
	945	+ [CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
	946	+ [CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
	947	+ [CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
	948	+ [CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
	949	+ [CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
	950	+ [CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
	951	+ [CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
	952	+ [CIF_REG_MIPI_FRAME_SIZE_ID0] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID0),
	953	+ [CIF_REG_MIPI_FRAME_SIZE_ID1] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID1),
	954	+ [CIF_REG_MIPI_FRAME_SIZE_ID2] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID2),
	955	+ [CIF_REG_MIPI_FRAME_SIZE_ID3] = CIF_REG(CSI_MIPI0_FRAME_SIZE_ID3),
	956	+ [CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
	957	+
	958	+ [CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
	959	+ [CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
	960	+ [CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
	961	+
	962	+ [CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
	963	+ [CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
	964	+ [CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
	965	+ [CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
	966	+ [CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
	967	+ [CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
	968	+
	969	+ [CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
	970	+ [CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
	971	+ [CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
	972	+};
	973	+
600	974	static const struct rkcif_hw_match_data px30_cif_match_data = {
601	975	.chip_id = CHIP_PX30_CIF,
602	976	.clks = px30_cif_clks,
..	..	@@ -678,6 +1052,32 @@
678	1052	.cif_regs = rk3568_cif_regs,
679	1053	};
680	1054
	1055	+static const struct rkcif_hw_match_data rk3588_cif_match_data = {
	1056	+ .chip_id = CHIP_RK3588_CIF,
	1057	+ .clks = rk3588_cif_clks,
	1058	+ .clks_num = ARRAY_SIZE(rk3588_cif_clks),
	1059	+ .rsts = rk3588_cif_rsts,
	1060	+ .rsts_num = ARRAY_SIZE(rk3588_cif_rsts),
	1061	+ .cif_regs = rk3588_cif_regs,
	1062	+};
	1063	+
	1064	+static const struct rkcif_hw_match_data rv1106_cif_match_data = {
	1065	+ .chip_id = CHIP_RV1106_CIF,
	1066	+ .clks = rv1106_cif_clks,
	1067	+ .clks_num = ARRAY_SIZE(rv1106_cif_clks),
	1068	+ .rsts = rv1106_cif_rsts,
	1069	+ .rsts_num = ARRAY_SIZE(rv1106_cif_rsts),
	1070	+ .cif_regs = rv1106_cif_regs,
	1071	+};
	1072	+
	1073	+static const struct rkcif_hw_match_data rk3562_cif_match_data = {
	1074	+ .chip_id = CHIP_RK3562_CIF,
	1075	+ .clks = rk3562_cif_clks,
	1076	+ .clks_num = ARRAY_SIZE(rk3562_cif_clks),
	1077	+ .rsts = rk3562_cif_rsts,
	1078	+ .rsts_num = ARRAY_SIZE(rk3562_cif_rsts),
	1079	+ .cif_regs = rk3562_cif_regs,
	1080	+};
681	1081
682	1082	static const struct of_device_id rkcif_plat_of_match[] = {
683	1083	#ifdef CONFIG_CPU_PX30
..	..	@@ -722,6 +1122,12 @@
722	1122	.data = &rk3568_cif_match_data,
723	1123	},
724	1124	#endif
	1125	+#ifdef CONFIG_CPU_RK3588
	1126	+ {
	1127	+ .compatible = "rockchip,rk3588-cif",
	1128	+ .data = &rk3588_cif_match_data,
	1129	+ },
	1130	+#endif
725	1131	#ifdef CONFIG_CPU_RV1126
726	1132	{
727	1133	.compatible = "rockchip,rv1126-cif",
..	..	@@ -732,6 +1138,18 @@
732	1138	.data = &rv1126_cif_lite_match_data,
733	1139	},
734	1140	#endif
	1141	+#ifdef CONFIG_CPU_RV1106
	1142	+ {
	1143	+ .compatible = "rockchip,rv1106-cif",
	1144	+ .data = &rv1106_cif_match_data,
	1145	+ },
	1146	+#endif
	1147	+#ifdef CONFIG_CPU_RK3562
	1148	+ {
	1149	+ .compatible = "rockchip,rk3562-cif",
	1150	+ .data = &rk3562_cif_match_data,
	1151	+ },
	1152	+#endif
735	1153	{},
736	1154	};
737	1155
..	..	@@ -739,16 +1157,32 @@
739	1157	{
740	1158	struct device *dev = ctx;
741	1159	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
	1160	+ unsigned int intstat_glb = 0;
	1161	+ u64 irq_start, irq_stop;
742	1162	int i;
743		- struct rkcif_device *tmp_dev = NULL;
744	1163
745		- for (i = 0; i < cif_hw->dev_num; i++) {
746		- tmp_dev = cif_hw->cif_dev[i];
747		- if (tmp_dev->isr_hdl &&
748		- (atomic_read(&tmp_dev->pipe.stream_cnt) != 0))
749		- tmp_dev->isr_hdl(irq, tmp_dev);
	1164	+ irq_start = ktime_get_ns();
	1165	+ if (cif_hw->chip_id >= CHIP_RK3588_CIF) {
	1166	+ intstat_glb = rkcif_irq_global(cif_hw->cif_dev[0]);
	1167	+ if (intstat_glb)
	1168	+ rkcif_write_register(cif_hw->cif_dev[0], CIF_REG_GLB_INTST, intstat_glb);
750	1169	}
751	1170
	1171	+ for (i = 0; i < cif_hw->dev_num; i++) {
	1172	+ if (cif_hw->cif_dev[i]->isr_hdl) {
	1173	+ cif_hw->cif_dev[i]->isr_hdl(irq, cif_hw->cif_dev[i]);
	1174	+ if (cif_hw->cif_dev[i]->err_state &&
	1175	+ (!work_busy(&cif_hw->cif_dev[i]->err_state_work.work))) {
	1176	+ cif_hw->cif_dev[i]->err_state_work.err_state = cif_hw->cif_dev[i]->err_state;
	1177	+ cif_hw->cif_dev[i]->err_state = 0;
	1178	+ schedule_work(&cif_hw->cif_dev[i]->err_state_work.work);
	1179	+ }
	1180	+ if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb)
	1181	+ rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb);
	1182	+ }
	1183	+ }
	1184	+ irq_stop = ktime_get_ns();
	1185	+ cif_hw->irq_time = irq_stop - irq_start;
752	1186	return IRQ_HANDLED;
753	1187	}
754	1188
..	..	@@ -783,17 +1217,14 @@
783	1217
784	1218	static void rkcif_iommu_cleanup(struct rkcif_hw *cif_hw)
785	1219	{
786		- if (cif_hw->domain)
787		- iommu_detach_device(cif_hw->domain, cif_hw->dev);
	1220	+ if (cif_hw->iommu_en)
	1221	+ rockchip_iommu_disable(cif_hw->dev);
788	1222	}
789	1223
790	1224	static void rkcif_iommu_enable(struct rkcif_hw *cif_hw)
791	1225	{
792		- if (!cif_hw->domain)
793		- cif_hw->domain = iommu_get_domain_for_dev(cif_hw->dev);
794		-
795		- if (cif_hw->domain)
796		- iommu_attach_device(cif_hw->domain, cif_hw->dev);
	1226	+ if (cif_hw->iommu_en)
	1227	+ rockchip_iommu_enable(cif_hw->dev);
797	1228	}
798	1229
799	1230	static inline bool is_iommu_enable(struct device *dev)
..	..	@@ -833,81 +1264,49 @@
833	1264	rkcif_iommu_enable(cif_hw);
834	1265	}
835	1266
836		-static char *rkcif_get_monitor_mode(enum rkcif_monitor_mode mode)
	1267	+static int rkcif_get_efuse_value(struct device_node np, char porp_name,
	1268	+ u8 *value)
837	1269	{
838		- switch (mode) {
839		- case RKCIF_MONITOR_MODE_IDLE:
840		- return "idle";
841		- case RKCIF_MONITOR_MODE_CONTINUE:
842		- return "continue";
843		- case RKCIF_MONITOR_MODE_TRIGGER:
844		- return "trigger";
845		- case RKCIF_MONITOR_MODE_HOTPLUG:
846		- return "hotplug";
847		- default:
848		- return "unknown";
849		- }
	1270	+ struct nvmem_cell *cell;
	1271	+ unsigned char *buf;
	1272	+ size_t len;
	1273	+
	1274	+ cell = of_nvmem_cell_get(np, porp_name);
	1275	+ if (IS_ERR(cell))
	1276	+ return PTR_ERR(cell);
	1277	+
	1278	+ buf = (unsigned char *)nvmem_cell_read(cell, &len);
	1279	+
	1280	+ nvmem_cell_put(cell);
	1281	+
	1282	+ if (IS_ERR(buf))
	1283	+ return PTR_ERR(buf);
	1284	+
	1285	+ *value = buf[0];
	1286	+
	1287	+ kfree(buf);
	1288	+
	1289	+ return 0;
850	1290	}
851	1291
852		-static void rkcif_init_reset_timer(struct rkcif_hw *hw)
	1292	+static int rkcif_get_speciand_package_number(struct device_node *np)
853	1293	{
854		- struct device_node *node = hw->dev->of_node;
855		- struct rkcif_hw_timer *hw_timer = &hw->hw_timer;
856		- u32 para[8];
857		- int i;
	1294	+ u8 spec = 0, package = 0, low = 0, high = 0;
858	1295
859		- if (!of_property_read_u32_array(node,
860		- OF_CIF_MONITOR_PARA,
861		- para,
862		- CIF_MONITOR_PARA_NUM)) {
863		- for (i = 0; i < CIF_MONITOR_PARA_NUM; i++) {
864		- if (i == 0) {
865		- hw_timer->monitor_mode = para[0];
866		- dev_info(hw->dev,
867		- "%s: timer monitor mode:%s\n",
868		- __func__, rkcif_get_monitor_mode(hw_timer->monitor_mode));
869		- }
	1296	+ if (rkcif_get_efuse_value(np, "specification", &spec))
	1297	+ return -EINVAL;
	1298	+ if (rkcif_get_efuse_value(np, "package_low", &low))
	1299	+ return -EINVAL;
	1300	+ if (rkcif_get_efuse_value(np, "package_high", &high))
	1301	+ return -EINVAL;
870	1302
871		- if (i == 1) {
872		- hw_timer->monitor_cycle = para[1];
873		- dev_info(hw->dev,
874		- "timer of monitor cycle:%d\n",
875		- hw_timer->monitor_cycle);
876		- }
	1303	+ package = ((high & 0x1) << 3) \| low;
877	1304
878		- if (i == 2) {
879		- hw_timer->err_time_interval = para[2];
880		- dev_info(hw->dev,
881		- "timer err time for keeping:%d ms\n",
882		- hw_timer->err_time_interval);
883		- }
	1305	+ /* RK3588S */
	1306	+ if (spec == 0x13)
	1307	+ return package;
884	1308
885		- if (i == 3) {
886		- hw_timer->err_ref_cnt = para[3];
887		- dev_info(hw->dev,
888		- "timer err ref val for resetting:%d\n",
889		- hw_timer->err_ref_cnt);
890		- }
891		-
892		- if (i == 4) {
893		- hw_timer->is_reset_by_user = para[4];
894		- dev_info(hw->dev,
895		- "reset by user:%d\n",
896		- hw_timer->is_reset_by_user);
897		- }
898		- }
899		- } else {
900		- hw_timer->monitor_mode = RKCIF_MONITOR_MODE_IDLE;
901		- hw_timer->err_time_interval = 0xffffffff;
902		- hw_timer->monitor_cycle = 0xffffffff;
903		- hw_timer->err_ref_cnt = 0xffffffff;
904		- hw_timer->is_reset_by_user = 0;
905		- }
906		-
907		- hw_timer->is_running = false;
908		- spin_lock_init(&hw_timer->timer_lock);
909		- hw->reset_info.is_need_reset = 0;
910		- timer_setup(&hw_timer->timer, rkcif_reset_watchdog_timer_handler, 0);
	1309	+ return -EINVAL;
911	1310	}
912	1311
913	1312	static int rkcif_plat_hw_probe(struct platform_device *pdev)
..	..	@@ -921,6 +1320,9 @@
921	1320	const struct rkcif_hw_match_data *data;
922	1321	struct resource *res;
923	1322	int i, ret, irq;
	1323	+ bool is_mem_reserved = false;
	1324	+ struct notifier_block *notifier;
	1325	+ int package = 0;
924	1326
925	1327	match = of_match_node(rkcif_plat_of_match, node);
926	1328	if (IS_ERR(match))
..	..	@@ -934,6 +1336,13 @@
934	1336	dev_set_drvdata(dev, cif_hw);
935	1337	cif_hw->dev = dev;
936	1338
	1339	+ package = rkcif_get_speciand_package_number(node);
	1340	+ if (package == 0x2) {
	1341	+ cif_hw->is_rk3588s2 = true;
	1342	+ dev_info(dev, "attach rk3588s2\n");
	1343	+ } else {
	1344	+ cif_hw->is_rk3588s2 = false;
	1345	+ }
937	1346	irq = platform_get_irq(pdev, 0);
938	1347	if (irq < 0)
939	1348	return irq;
..	..	@@ -949,10 +1358,7 @@
949	1358	cif_hw->irq = irq;
950	1359	cif_hw->match_data = data;
951	1360	cif_hw->chip_id = data->chip_id;
952		- if (data->chip_id == CHIP_RK1808_CIF \|\|
953		- data->chip_id == CHIP_RV1126_CIF \|\|
954		- data->chip_id == CHIP_RV1126_CIF_LITE \|\|
955		- data->chip_id == CHIP_RK3568_CIF) {
	1361	+ if (data->chip_id >= CHIP_RK1808_CIF) {
956	1362	res = platform_get_resource_byname(pdev,
957	1363	IORESOURCE_MEM,
958	1364	"cif_regs");
..	..	@@ -972,6 +1378,11 @@
972	1378	cif_hw->base_addr = devm_ioremap_resource(dev, res);
973	1379	if (IS_ERR(cif_hw->base_addr))
974	1380	return PTR_ERR(cif_hw->base_addr);
	1381	+ }
	1382	+
	1383	+ if (of_property_read_bool(np, "rockchip,android-usb-camerahal-enable")) {
	1384	+ dev_info(dev, "config cif adapt to android usb camera hal!\n");
	1385	+ cif_hw->adapt_to_usbcamerahal = true;
975	1386	}
976	1387
977	1388	cif_hw->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
..	..	@@ -1003,25 +1414,32 @@
1003	1414	if (data->rsts[i])
1004	1415	rst = devm_reset_control_get(dev, data->rsts[i]);
1005	1416	if (IS_ERR(rst)) {
	1417	+ cif_hw->cif_rst[i] = NULL;
1006	1418	dev_err(dev, "failed to get %s\n", data->rsts[i]);
1007		- return PTR_ERR(rst);
	1419	+ } else {
	1420	+ cif_hw->cif_rst[i] = rst;
1008	1421	}
1009		- cif_hw->cif_rst[i] = rst;
1010	1422	}
1011	1423
1012	1424	cif_hw->cif_regs = data->cif_regs;
1013	1425
1014		- cif_hw->iommu_en = is_iommu_enable(dev);
1015		- if (!cif_hw->iommu_en) {
1016		- ret = of_reserved_mem_device_init(dev);
1017		- if (ret)
1018		- dev_info(dev, "No reserved memory region assign to CIF\n");
1019		- }
	1426	+ cif_hw->is_dma_sg_ops = true;
	1427	+ cif_hw->is_dma_contig = true;
	1428	+ mutex_init(&cif_hw->dev_lock);
	1429	+ spin_lock_init(&cif_hw->group_lock);
	1430	+ atomic_set(&cif_hw->power_cnt, 0);
1020	1431
1021		- if (data->chip_id != CHIP_RK1808_CIF &&
1022		- data->chip_id != CHIP_RV1126_CIF &&
1023		- data->chip_id != CHIP_RV1126_CIF_LITE &&
1024		- data->chip_id != CHIP_RK3568_CIF) {
	1432	+ cif_hw->iommu_en = is_iommu_enable(dev);
	1433	+ ret = of_reserved_mem_device_init(dev);
	1434	+ if (ret) {
	1435	+ is_mem_reserved = false;
	1436	+ dev_info(dev, "No reserved memory region assign to CIF\n");
	1437	+ }
	1438	+ if (cif_hw->iommu_en && !is_mem_reserved)
	1439	+ cif_hw->is_dma_contig = false;
	1440	+ cif_hw->mem_ops = &vb2_cma_sg_memops;
	1441	+
	1442	+ if (data->chip_id < CHIP_RK1808_CIF) {
1025	1443	cif_dev = devm_kzalloc(dev, sizeof(*cif_dev), GFP_KERNEL);
1026	1444	if (!cif_dev)
1027	1445	return -ENOMEM;
..	..	@@ -1036,20 +1454,20 @@
1036	1454	return ret;
1037	1455	}
1038	1456
1039		- rkcif_hw_soft_reset(cif_hw, true);
1040		-
1041	1457	mutex_init(&cif_hw->dev_lock);
1042		- spin_lock_init(&cif_hw->spin_lock);
1043	1458
1044	1459	pm_runtime_enable(&pdev->dev);
1045		- rkcif_init_reset_timer(cif_hw);
1046	1460
1047		- if (data->chip_id == CHIP_RK1808_CIF \|\|
1048		- data->chip_id == CHIP_RV1126_CIF \|\|
1049		- data->chip_id == CHIP_RK3568_CIF) {
	1461	+ if (data->chip_id >= CHIP_RK1808_CIF &&
	1462	+ data->chip_id != CHIP_RV1126_CIF_LITE) {
1050	1463	platform_driver_register(&rkcif_plat_drv);
1051	1464	platform_driver_register(&rkcif_subdev_driver);
1052	1465	}
	1466	+
	1467	+ notifier = &cif_hw->reset_notifier;
	1468	+ notifier->priority = 1;
	1469	+ notifier->notifier_call = rkcif_reset_notifier;
	1470	+ rkcif_csi2_register_notifier(notifier);
1053	1471
1054	1472	return 0;
1055	1473	}
..	..	@@ -1063,19 +1481,53 @@
1063	1481	rkcif_iommu_cleanup(cif_hw);
1064	1482
1065	1483	mutex_destroy(&cif_hw->dev_lock);
1066		- if (cif_hw->chip_id != CHIP_RK1808_CIF &&
1067		- cif_hw->chip_id != CHIP_RV1126_CIF &&
1068		- cif_hw->chip_id != CHIP_RV1126_CIF_LITE &&
1069		- cif_hw->chip_id != CHIP_RK3568_CIF)
	1484	+ if (cif_hw->chip_id < CHIP_RK1808_CIF)
1070	1485	rkcif_plat_uninit(cif_hw->cif_dev[0]);
1071		- del_timer_sync(&cif_hw->hw_timer.timer);
	1486	+
	1487	+ rkcif_csi2_unregister_notifier(&cif_hw->reset_notifier);
	1488	+
1072	1489	return 0;
	1490	+}
	1491	+
	1492	+static void rkcif_hw_shutdown(struct platform_device *pdev)
	1493	+{
	1494	+ struct rkcif_hw *cif_hw = platform_get_drvdata(pdev);
	1495	+ struct rkcif_device *cif_dev = NULL;
	1496	+ int i = 0;
	1497	+
	1498	+ if (pm_runtime_get_if_in_use(&pdev->dev) <= 0)
	1499	+ return;
	1500	+
	1501	+ if (cif_hw->chip_id == CHIP_RK3588_CIF \|\|
	1502	+ cif_hw->chip_id == CHIP_RV1106_CIF \|\|
	1503	+ cif_hw->chip_id == CHIP_RK3562_CIF) {
	1504	+ write_cif_reg(cif_hw->base_addr, 0, 0);
	1505	+ } else {
	1506	+ for (i = 0; i < cif_hw->dev_num; i++) {
	1507	+ cif_dev = cif_hw->cif_dev[i];
	1508	+ if (atomic_read(&cif_dev->pipe.stream_cnt)) {
	1509	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	1510	+ rkcif_write_register(cif_dev,
	1511	+ CIF_REG_MIPI_LVDS_CTRL,
	1512	+ 0);
	1513	+ else
	1514	+ rkcif_write_register(cif_dev,
	1515	+ CIF_REG_DVP_CTRL,
	1516	+ 0);
	1517	+ }
	1518	+ }
	1519	+ }
	1520	+ if (cif_hw->irq > 0)
	1521	+ disable_irq(cif_hw->irq);
	1522	+ pm_runtime_put(&pdev->dev);
1073	1523	}
1074	1524
1075	1525	static int __maybe_unused rkcif_runtime_suspend(struct device *dev)
1076	1526	{
1077	1527	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1078	1528
	1529	+ if (atomic_dec_return(&cif_hw->power_cnt))
	1530	+ return 0;
1079	1531	rkcif_disable_sys_clk(cif_hw);
1080	1532
1081	1533	return pinctrl_pm_select_sleep_state(dev);
..	..	@@ -1086,17 +1538,49 @@
1086	1538	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1087	1539	int ret;
1088	1540
	1541	+ if (atomic_inc_return(&cif_hw->power_cnt) > 1)
	1542	+ return 0;
1089	1543	ret = pinctrl_pm_select_default_state(dev);
1090	1544	if (ret < 0)
1091	1545	return ret;
1092	1546	rkcif_enable_sys_clk(cif_hw);
	1547	+ rkcif_hw_soft_reset(cif_hw, true);
	1548	+
	1549	+ return 0;
	1550	+}
	1551	+
	1552	+static int __maybe_unused rkcif_sleep_suspend(struct device *dev)
	1553	+{
	1554	+ struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
	1555	+
	1556	+ if (atomic_read(&cif_hw->power_cnt) == 0)
	1557	+ return 0;
	1558	+
	1559	+ rkcif_disable_sys_clk(cif_hw);
	1560	+
	1561	+ return pinctrl_pm_select_sleep_state(dev);
	1562	+}
	1563	+
	1564	+static int __maybe_unused rkcif_sleep_resume(struct device *dev)
	1565	+{
	1566	+ struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
	1567	+ int ret;
	1568	+
	1569	+ if (atomic_read(&cif_hw->power_cnt) == 0)
	1570	+ return 0;
	1571	+
	1572	+ ret = pinctrl_pm_select_default_state(dev);
	1573	+ if (ret < 0)
	1574	+ return ret;
	1575	+ rkcif_enable_sys_clk(cif_hw);
	1576	+ rkcif_hw_soft_reset(cif_hw, true);
1093	1577
1094	1578	return 0;
1095	1579	}
1096	1580
1097	1581	static const struct dev_pm_ops rkcif_plat_pm_ops = {
1098		- SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1099		- pm_runtime_force_resume)
	1582	+ SET_LATE_SYSTEM_SLEEP_PM_OPS(rkcif_sleep_suspend,
	1583	+ rkcif_sleep_resume)
1100	1584	SET_RUNTIME_PM_OPS(rkcif_runtime_suspend, rkcif_runtime_resume, NULL)
1101	1585	};
1102	1586
..	..	@@ -1108,15 +1592,17 @@
1108	1592	},
1109	1593	.probe = rkcif_plat_hw_probe,
1110	1594	.remove = rkcif_plat_remove,
	1595	+ .shutdown = rkcif_hw_shutdown,
1111	1596	};
1112	1597
1113		-static int __init rk_cif_plat_drv_init(void)
	1598	+int rk_cif_plat_drv_init(void)
1114	1599	{
1115	1600	int ret;
1116	1601
1117	1602	ret = platform_driver_register(&rkcif_hw_plat_drv);
1118	1603	if (ret)
1119	1604	return ret;
	1605	+ rkcif_csi2_hw_plat_drv_init();
1120	1606	return rkcif_csi2_plat_drv_init();
1121	1607	}
1122	1608
..	..	@@ -1124,9 +1610,16 @@
1124	1610	{
1125	1611	platform_driver_unregister(&rkcif_hw_plat_drv);
1126	1612	rkcif_csi2_plat_drv_exit();
	1613	+ rkcif_csi2_hw_plat_drv_exit();
1127	1614	}
1128	1615
	1616	+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
	1617	+subsys_initcall(rk_cif_plat_drv_init);
	1618	+#else
	1619	+#if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
1129	1620	module_init(rk_cif_plat_drv_init);
	1621	+#endif
	1622	+#endif
1130	1623	module_exit(rk_cif_plat_drv_exit);
1131	1624
1132	1625	MODULE_AUTHOR("Rockchip Camera/ISP team");