change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
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@@ -241,8 +241,27 @@
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 	return 0;
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 }
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+const struct nvkm_falcon_func
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+gt215_pmu_flcn = {
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+	.debug = 0xc08,
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+	.fbif = 0xe00,
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+	.load_imem = nvkm_falcon_v1_load_imem,
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+	.load_dmem = nvkm_falcon_v1_load_dmem,
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+	.read_dmem = nvkm_falcon_v1_read_dmem,
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+	.bind_context = nvkm_falcon_v1_bind_context,
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+	.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
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+	.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
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+	.set_start_addr = nvkm_falcon_v1_set_start_addr,
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+	.start = nvkm_falcon_v1_start,
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+	.enable = nvkm_falcon_v1_enable,
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+	.disable = nvkm_falcon_v1_disable,
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+	.cmdq = { 0x4a0, 0x4b0, 4 },
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+	.msgq = { 0x4c8, 0x4cc, 0 },
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+};
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+
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 static const struct nvkm_pmu_func
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 gt215_pmu = {
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+	.flcn = &gt215_pmu_flcn,
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 	.code.data = gt215_pmu_code,
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 	.code.size = sizeof(gt215_pmu_code),
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 	.data.data = gt215_pmu_data,
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@@ -256,8 +275,14 @@
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 	.recv = gt215_pmu_recv,
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 };
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+static const struct nvkm_pmu_fwif
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+gt215_pmu_fwif[] = {
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+	{ -1, gf100_pmu_nofw, &gt215_pmu },
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+	{}
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+};
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+
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 int
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 gt215_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
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 {
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-	return nvkm_pmu_new_(&gt215_pmu, device, index, ppmu);
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+	return nvkm_pmu_new_(gt215_pmu_fwif, device, index, ppmu);
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 }