change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c
..
..
@@ -24,7 +24,81 @@
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 #include "gf100.h"
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 #include "ram.h"
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+#include <core/firmware.h>
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 #include <core/memory.h>
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+#include <nvfw/fw.h>
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+#include <nvfw/hs.h>
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+#include <engine/nvdec.h>
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+
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+int
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+gp102_fb_vpr_scrub(struct nvkm_fb *fb)
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+{
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+	struct nvkm_subdev *subdev = &fb->subdev;
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+	struct nvkm_device *device = subdev->device;
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+	struct nvkm_falcon *falcon = &device->nvdec[0]->falcon;
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+	struct nvkm_blob *blob = &fb->vpr_scrubber;
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+	const struct nvfw_bin_hdr *hsbin_hdr;
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+	const struct nvfw_hs_header *fw_hdr;
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+	const struct nvfw_hs_load_header *lhdr;
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+	void *scrub_data;
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+	u32 patch_loc, patch_sig;
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+	int ret;
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+
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+	nvkm_falcon_get(falcon, subdev);
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+
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+	hsbin_hdr = nvfw_bin_hdr(subdev, blob->data);
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+	fw_hdr = nvfw_hs_header(subdev, blob->data + hsbin_hdr->header_offset);
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+	lhdr = nvfw_hs_load_header(subdev, blob->data + fw_hdr->hdr_offset);
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+	scrub_data = blob->data + hsbin_hdr->data_offset;
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+
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+	patch_loc = *(u32 *)(blob->data + fw_hdr->patch_loc);
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+	patch_sig = *(u32 *)(blob->data + fw_hdr->patch_sig);
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+	if (falcon->debug) {
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+		memcpy(scrub_data + patch_loc,
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+		       blob->data + fw_hdr->sig_dbg_offset + patch_sig,
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+		       fw_hdr->sig_dbg_size);
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+	} else {
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+		memcpy(scrub_data + patch_loc,
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+		       blob->data + fw_hdr->sig_prod_offset + patch_sig,
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+		       fw_hdr->sig_prod_size);
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+	}
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+
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+	nvkm_falcon_reset(falcon);
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+	nvkm_falcon_bind_context(falcon, NULL);
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+
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+	nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off,
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+			      lhdr->non_sec_code_size,
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+			      lhdr->non_sec_code_off >> 8, 0, false);
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+	nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0],
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+			      ALIGN(lhdr->apps[0], 0x100),
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+			      lhdr->apps[1],
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+			      lhdr->apps[0] >> 8, 0, true);
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+	nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0,
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+			      lhdr->data_size, 0);
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+
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+	nvkm_falcon_set_start_addr(falcon, 0x0);
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+	nvkm_falcon_start(falcon);
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+
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+	ret = nvkm_falcon_wait_for_halt(falcon, 500);
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+	if (ret < 0) {
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+		ret = -ETIMEDOUT;
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+		goto end;
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+	}
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+
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+	/* put nvdec in clean state - without reset it will remain in HS mode */
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+	nvkm_falcon_reset(falcon);
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+end:
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+	nvkm_falcon_put(falcon, subdev);
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+	return ret;
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+}
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+
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+bool
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+gp102_fb_vpr_scrub_required(struct nvkm_fb *fb)
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+{
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+	struct nvkm_device *device = fb->subdev.device;
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+	nvkm_wr32(device, 0x100cd0, 0x2);
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+	return (nvkm_rd32(device, 0x100cd0) & 0x00000010) != 0;
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+}
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102
 
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 static const struct nvkm_fb_func
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 gp102_fb = {
..
..
@@ -33,11 +107,32 @@
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 	.init = gp100_fb_init,
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 	.init_remapper = gp100_fb_init_remapper,
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 	.init_page = gm200_fb_init_page,
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+	.vpr.scrub_required = gp102_fb_vpr_scrub_required,
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+	.vpr.scrub = gp102_fb_vpr_scrub,
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112
 	.ram_new = gp100_ram_new,
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 };
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 int
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+gp102_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
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+	      int index, struct nvkm_fb **pfb)
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+{
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+	int ret = gf100_fb_new_(func, device, index, pfb);
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+	if (ret)
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+		return ret;
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+
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+	nvkm_firmware_load_blob(&(*pfb)->subdev, "nvdec/scrubber", "", 0,
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+				&(*pfb)->vpr_scrubber);
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+	return 0;
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+}
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+
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+int
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 gp102_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
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 {
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-	return gf100_fb_new_(&gp102_fb, device, index, pfb);
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+	return gp102_fb_new_(&gp102_fb, device, index, pfb);
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132
 }
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+
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+MODULE_FIRMWARE("nvidia/gp102/nvdec/scrubber.bin");
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+MODULE_FIRMWARE("nvidia/gp104/nvdec/scrubber.bin");
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+MODULE_FIRMWARE("nvidia/gp106/nvdec/scrubber.bin");
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+MODULE_FIRMWARE("nvidia/gp107/nvdec/scrubber.bin");
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+MODULE_FIRMWARE("nvidia/gp108/nvdec/scrubber.bin");