change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/gpu/drm/nouveau/dispnv04/overlay.c
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@@ -23,7 +23,6 @@
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  * written by Arthur Huillet.
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  */
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-#include <drm/drmP.h>
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 #include <drm/drm_crtc.h>
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 #include <drm/drm_fourcc.h>
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@@ -32,6 +31,7 @@
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 #include "nouveau_bo.h"
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 #include "nouveau_connector.h"
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 #include "nouveau_display.h"
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+#include "nouveau_gem.h"
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 #include "nvreg.h"
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 #include "disp.h"
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@@ -121,9 +121,9 @@
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 	struct nvif_object *dev = &drm->client.device.object;
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 	struct nouveau_plane *nv_plane =
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 		container_of(plane, struct nouveau_plane, base);
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-	struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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 	struct nouveau_bo *cur = nv_plane->cur;
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+	struct nouveau_bo *nvbo;
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 	bool flip = nv_plane->flip;
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 	int soff = NV_PCRTC0_SIZE * nv_crtc->index;
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 	int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;
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@@ -141,17 +141,18 @@
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 	if (ret)
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 		return ret;
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-	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);
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+	nvbo = nouveau_gem_object(fb->obj[0]);
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+	ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false);
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 	if (ret)
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 		return ret;
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-	nv_plane->cur = nv_fb->nvbo;
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+	nv_plane->cur = nvbo;
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 	nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
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 	nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
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 	nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0);
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-	nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset);
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+	nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nvbo->offset);
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 	nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w);
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 	nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x);
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 	nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
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@@ -173,7 +174,7 @@
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 	if (format & NV_PVIDEO_FORMAT_PLANAR) {
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 		nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
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 		nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
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-			nv_fb->nvbo->bo.offset + fb->offsets[1]);
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+			nvbo->offset + fb->offsets[1]);
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 	}
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 	nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]);
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 	nvif_wr32(dev, NV_PVIDEO_STOP, 0);
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@@ -369,8 +370,8 @@
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 	struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object;
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 	struct nouveau_plane *nv_plane =
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 		container_of(plane, struct nouveau_plane, base);
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-	struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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 	struct nouveau_bo *cur = nv_plane->cur;
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+	struct nouveau_bo *nvbo;
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 	uint32_t overlay = 1;
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 	int brightness = (nv_plane->brightness - 512) * 62 / 512;
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 	int ret, i;
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@@ -385,11 +386,12 @@
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 	if (ret)
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 		return ret;
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-	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);
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+	nvbo = nouveau_gem_object(fb->obj[0]);
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+	ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false);
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 	if (ret)
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 		return ret;
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-	nv_plane->cur = nv_fb->nvbo;
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+	nv_plane->cur = nvbo;
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 	nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0);
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 	nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0);
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@@ -397,7 +399,7 @@
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 	for (i = 0; i < 2; i++) {
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 		nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,
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-			  nv_fb->nvbo->bo.offset);
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+			  nvbo->offset);
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 		nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i,
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 			  fb->pitches[0]);
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 		nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);