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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/drivers/gpu/drm/msm/adreno/adreno_device.c
....@@ -1,20 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2013-2014 Red Hat
34  * Author: Rob Clark <robdclark@gmail.com>
45  *
56  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
6
- *
7
- * This program is free software; you can redistribute it and/or modify it
8
- * under the terms of the GNU General Public License version 2 as published by
9
- * the Free Software Foundation.
10
- *
11
- * This program is distributed in the hope that it will be useful, but WITHOUT
12
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14
- * more details.
15
- *
16
- * You should have received a copy of the GNU General Public License along with
17
- * this program.  If not, see <http://www.gnu.org/licenses/>.
187  */
198 
209 #include "adreno_gpu.h"
....@@ -25,8 +14,45 @@
2514 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
2615 module_param_named(hang_debug, hang_debug, bool, 0600);
2716 
17
+bool snapshot_debugbus = false;
18
+MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
19
+module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
20
+
2821 static const struct adreno_info gpulist[] = {
2922 	{
23
+		.rev   = ADRENO_REV(2, 0, 0, 0),
24
+		.revn  = 200,
25
+		.name  = "A200",
26
+		.fw = {
27
+			[ADRENO_FW_PM4] = "yamato_pm4.fw",
28
+			[ADRENO_FW_PFP] = "yamato_pfp.fw",
29
+		},
30
+		.gmem  = SZ_256K,
31
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
32
+		.init  = a2xx_gpu_init,
33
+	}, { /* a200 on i.mx51 has only 128kib gmem */
34
+		.rev   = ADRENO_REV(2, 0, 0, 1),
35
+		.revn  = 201,
36
+		.name  = "A200",
37
+		.fw = {
38
+			[ADRENO_FW_PM4] = "yamato_pm4.fw",
39
+			[ADRENO_FW_PFP] = "yamato_pfp.fw",
40
+		},
41
+		.gmem  = SZ_128K,
42
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
43
+		.init  = a2xx_gpu_init,
44
+	}, {
45
+		.rev   = ADRENO_REV(2, 2, 0, ANY_ID),
46
+		.revn  = 220,
47
+		.name  = "A220",
48
+		.fw = {
49
+			[ADRENO_FW_PM4] = "leia_pm4_470.fw",
50
+			[ADRENO_FW_PFP] = "leia_pfp_470.fw",
51
+		},
52
+		.gmem  = SZ_512K,
53
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
54
+		.init  = a2xx_gpu_init,
55
+	}, {
3056 		.rev   = ADRENO_REV(3, 0, 5, ANY_ID),
3157 		.revn  = 305,
3258 		.name  = "A305",
....@@ -71,6 +97,17 @@
7197 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
7298 		.init  = a3xx_gpu_init,
7399 	}, {
100
+		.rev   = ADRENO_REV(4, 0, 5, ANY_ID),
101
+		.revn  = 405,
102
+		.name  = "A405",
103
+		.fw = {
104
+			[ADRENO_FW_PM4] = "a420_pm4.fw",
105
+			[ADRENO_FW_PFP] = "a420_pfp.fw",
106
+		},
107
+		.gmem  = SZ_256K,
108
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
109
+		.init  = a4xx_gpu_init,
110
+	}, {
74111 		.rev   = ADRENO_REV(4, 2, 0, ANY_ID),
75112 		.revn  = 420,
76113 		.name  = "A420",
....@@ -93,6 +130,21 @@
93130 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
94131 		.init  = a4xx_gpu_init,
95132 	}, {
133
+		.rev   = ADRENO_REV(5, 1, 0, ANY_ID),
134
+		.revn = 510,
135
+		.name = "A510",
136
+		.fw = {
137
+			[ADRENO_FW_PM4] = "a530_pm4.fw",
138
+			[ADRENO_FW_PFP] = "a530_pfp.fw",
139
+		},
140
+		.gmem = SZ_256K,
141
+		/*
142
+		 * Increase inactive period to 250 to avoid bouncing
143
+		 * the GDSC which appears to make it grumpy
144
+		 */
145
+		.inactive_period = 250,
146
+		.init = a5xx_gpu_init,
147
+	}, {
96148 		.rev = ADRENO_REV(5, 3, 0, 2),
97149 		.revn = 530,
98150 		.name = "A530",
....@@ -112,6 +164,35 @@
112164 		.init = a5xx_gpu_init,
113165 		.zapfw = "a530_zap.mdt",
114166 	}, {
167
+		.rev = ADRENO_REV(5, 4, 0, 2),
168
+		.revn = 540,
169
+		.name = "A540",
170
+		.fw = {
171
+			[ADRENO_FW_PM4] = "a530_pm4.fw",
172
+			[ADRENO_FW_PFP] = "a530_pfp.fw",
173
+			[ADRENO_FW_GPMU] = "a540_gpmu.fw2",
174
+		},
175
+		.gmem = SZ_1M,
176
+		/*
177
+		 * Increase inactive period to 250 to avoid bouncing
178
+		 * the GDSC which appears to make it grumpy
179
+		 */
180
+		.inactive_period = 250,
181
+		.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
182
+		.init = a5xx_gpu_init,
183
+		.zapfw = "a540_zap.mdt",
184
+	}, {
185
+		.rev = ADRENO_REV(6, 1, 8, ANY_ID),
186
+		.revn = 618,
187
+		.name = "A618",
188
+		.fw = {
189
+			[ADRENO_FW_SQE] = "a630_sqe.fw",
190
+			[ADRENO_FW_GMU] = "a630_gmu.bin",
191
+		},
192
+		.gmem = SZ_512K,
193
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
194
+		.init = a6xx_gpu_init,
195
+	}, {
115196 		.rev = ADRENO_REV(6, 3, 0, ANY_ID),
116197 		.revn = 630,
117198 		.name = "A630",
....@@ -120,7 +201,36 @@
120201 			[ADRENO_FW_GMU] = "a630_gmu.bin",
121202 		},
122203 		.gmem = SZ_1M,
204
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
123205 		.init = a6xx_gpu_init,
206
+		.zapfw = "a630_zap.mdt",
207
+		.hwcg = a630_hwcg,
208
+	}, {
209
+		.rev = ADRENO_REV(6, 4, 0, ANY_ID),
210
+		.revn = 640,
211
+		.name = "A640",
212
+		.fw = {
213
+			[ADRENO_FW_SQE] = "a630_sqe.fw",
214
+			[ADRENO_FW_GMU] = "a640_gmu.bin",
215
+		},
216
+		.gmem = SZ_1M,
217
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
218
+		.init = a6xx_gpu_init,
219
+		.zapfw = "a640_zap.mdt",
220
+		.hwcg = a640_hwcg,
221
+	}, {
222
+		.rev = ADRENO_REV(6, 5, 0, ANY_ID),
223
+		.revn = 650,
224
+		.name = "A650",
225
+		.fw = {
226
+			[ADRENO_FW_SQE] = "a650_sqe.fw",
227
+			[ADRENO_FW_GMU] = "a650_gmu.bin",
228
+		},
229
+		.gmem = SZ_1M + SZ_128K,
230
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
231
+		.init = a6xx_gpu_init,
232
+		.zapfw = "a650_zap.mdt",
233
+		.hwcg = a650_hwcg,
124234 	},
125235 };
126236 
....@@ -139,6 +249,7 @@
139249 MODULE_FIRMWARE("qcom/a530_zap.b02");
140250 MODULE_FIRMWARE("qcom/a630_sqe.fw");
141251 MODULE_FIRMWARE("qcom/a630_gmu.bin");
252
+MODULE_FIRMWARE("qcom/a630_zap.mbn");
142253 
143254 static inline bool _rev_match(uint8_t entry, uint8_t id)
144255 {
....@@ -171,7 +282,7 @@
171282 	int ret;
172283 
173284 	if (pdev)
174
-		gpu = platform_get_drvdata(pdev);
285
+		gpu = dev_to_gpu(&pdev->dev);
175286 
176287 	if (!gpu) {
177288 		dev_err_once(dev->dev, "no GPU device was found\n");
....@@ -190,12 +301,16 @@
190301 	if (ret)
191302 		return NULL;
192303 
193
-	/* Make sure pm runtime is active and reset any previous errors */
194
-	pm_runtime_set_active(&pdev->dev);
304
+	/*
305
+	 * Now that we have firmware loaded, and are ready to begin
306
+	 * booting the gpu, go ahead and enable runpm:
307
+	 */
308
+	pm_runtime_enable(&pdev->dev);
195309 
196310 	ret = pm_runtime_get_sync(&pdev->dev);
197311 	if (ret < 0) {
198
-		dev_err(dev->dev, "Couldn't power up the GPU: %d\n", ret);
312
+		pm_runtime_put_sync(&pdev->dev);
313
+		DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
199314 		return NULL;
200315 	}
201316 
....@@ -204,7 +319,7 @@
204319 	mutex_unlock(&dev->struct_mutex);
205320 	pm_runtime_put_autosuspend(&pdev->dev);
206321 	if (ret) {
207
-		dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
322
+		DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
208323 		return NULL;
209324 	}
210325 
....@@ -237,7 +352,8 @@
237352 	if (ret == 0) {
238353 		unsigned int r, patch;
239354 
240
-		if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
355
+		if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
356
+		    sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
241357 			rev->core = r / 100;
242358 			r %= 100;
243359 			rev->major = r / 10;
....@@ -252,7 +368,7 @@
252368 	/* and if that fails, fall back to legacy "qcom,chipid" property: */
253369 	ret = of_property_read_u32(node, "qcom,chipid", &chipid);
254370 	if (ret) {
255
-		dev_err(dev, "could not parse qcom,chipid: %d\n", ret);
371
+		DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
256372 		return ret;
257373 	}
258374 
....@@ -273,6 +389,7 @@
273389 	static struct adreno_platform_config config = {};
274390 	const struct adreno_info *info;
275391 	struct drm_device *drm = dev_get_drvdata(master);
392
+	struct msm_drm_private *priv = drm->dev_private;
276393 	struct msm_gpu *gpu;
277394 	int ret;
278395 
....@@ -295,13 +412,13 @@
295412 	DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
296413 		config.rev.minor, config.rev.patchid);
297414 
415
+	priv->is_a2xx = config.rev.core == 2;
416
+
298417 	gpu = info->init(drm);
299418 	if (IS_ERR(gpu)) {
300419 		dev_warn(drm->dev, "failed to load adreno gpu\n");
301420 		return PTR_ERR(gpu);
302421 	}
303
-
304
-	dev_set_drvdata(dev, gpu);
305422 
306423 	return 0;
307424 }
....@@ -309,9 +426,9 @@
309426 static void adreno_unbind(struct device *dev, struct device *master,
310427 		void *data)
311428 {
312
-	struct msm_gpu *gpu = dev_get_drvdata(dev);
429
+	struct msm_gpu *gpu = dev_to_gpu(dev);
313430 
314
-	gpu->funcs->pm_suspend(gpu);
431
+	pm_runtime_force_suspend(dev);
315432 	gpu->funcs->destroy(gpu);
316433 
317434 	set_gpu_pdev(dev_get_drvdata(master), NULL);
....@@ -322,9 +439,37 @@
322439 		.unbind = adreno_unbind,
323440 };
324441 
442
+static void adreno_device_register_headless(void)
443
+{
444
+	/* on imx5, we don't have a top-level mdp/dpu node
445
+	 * this creates a dummy node for the driver for that case
446
+	 */
447
+	struct platform_device_info dummy_info = {
448
+		.parent = NULL,
449
+		.name = "msm",
450
+		.id = -1,
451
+		.res = NULL,
452
+		.num_res = 0,
453
+		.data = NULL,
454
+		.size_data = 0,
455
+		.dma_mask = ~0,
456
+	};
457
+	platform_device_register_full(&dummy_info);
458
+}
459
+
325460 static int adreno_probe(struct platform_device *pdev)
326461 {
327
-	return component_add(&pdev->dev, &a3xx_ops);
462
+
463
+	int ret;
464
+
465
+	ret = component_add(&pdev->dev, &a3xx_ops);
466
+	if (ret)
467
+		return ret;
468
+
469
+	if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
470
+		adreno_device_register_headless();
471
+
472
+	return 0;
328473 }
329474 
330475 static int adreno_remove(struct platform_device *pdev)
....@@ -336,6 +481,8 @@
336481 static const struct of_device_id dt_match[] = {
337482 	{ .compatible = "qcom,adreno" },
338483 	{ .compatible = "qcom,adreno-3xx" },
484
+	/* for compatibility with imx5 gpu: */
485
+	{ .compatible = "amd,imageon" },
339486 	/* for backwards compat w/ downstream kgsl DT files: */
340487 	{ .compatible = "qcom,kgsl-3d0" },
341488 	{}
....@@ -344,16 +491,14 @@
344491 #ifdef CONFIG_PM
345492 static int adreno_resume(struct device *dev)
346493 {
347
-	struct platform_device *pdev = to_platform_device(dev);
348
-	struct msm_gpu *gpu = platform_get_drvdata(pdev);
494
+	struct msm_gpu *gpu = dev_to_gpu(dev);
349495 
350496 	return gpu->funcs->pm_resume(gpu);
351497 }
352498 
353499 static int adreno_suspend(struct device *dev)
354500 {
355
-	struct platform_device *pdev = to_platform_device(dev);
356
-	struct msm_gpu *gpu = platform_get_drvdata(pdev);
501
+	struct msm_gpu *gpu = dev_to_gpu(dev);
357502 
358503 	return gpu->funcs->pm_suspend(gpu);
359504 }