change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
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@@ -4,15 +4,16 @@
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 #ifndef _A6XX_GMU_H_
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 #define _A6XX_GMU_H_
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+#include <linux/iopoll.h>
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 #include <linux/interrupt.h>
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 #include "msm_drv.h"
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 #include "a6xx_hfi.h"
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 struct a6xx_gmu_bo {
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+	struct drm_gem_object *obj;
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 	void *virt;
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 	size_t size;
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 	u64 iova;
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-	struct page **pages;
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 };
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 /*
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@@ -25,9 +26,6 @@
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 /* the GMU is coming up for the first time or back from a power collapse */
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 #define GMU_COLD_BOOT 1
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-
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-/* The GMU is being soft reset after a fault */
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-#define GMU_RESET 2
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 /*
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  * These define the level of control that the GMU has - the higher the number
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@@ -46,25 +44,31 @@
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 struct a6xx_gmu {
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 	struct device *dev;
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+	struct msm_gem_address_space *aspace;
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+
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 	void * __iomem mmio;
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-	void * __iomem pdc_mmio;
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+	void * __iomem rscc;
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 	int hfi_irq;
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 	int gmu_irq;
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-	struct regulator *gx;
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-
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-	struct iommu_domain *domain;
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-	u64 uncached_iova_base;
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+	struct device *gxpd;
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 	int idle_level;
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-	struct a6xx_gmu_bo *hfi;
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-	struct a6xx_gmu_bo *debug;
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+	struct a6xx_gmu_bo hfi;
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+	struct a6xx_gmu_bo debug;
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+	struct a6xx_gmu_bo icache;
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+	struct a6xx_gmu_bo dcache;
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+	struct a6xx_gmu_bo dummy;
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+	struct a6xx_gmu_bo log;
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 	int nr_clocks;
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 	struct clk_bulk_data *clocks;
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 	struct clk *core_clk;
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+
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+	/* current performance index set externally */
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+	int current_perf_index;
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 	int nr_gpu_freqs;
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 	unsigned long gpu_freqs[16];
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@@ -74,9 +78,13 @@
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 	unsigned long gmu_freqs[4];
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 	u32 cx_arc_votes[4];
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+	unsigned long freq;
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+
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 	struct a6xx_hfi_queue queues[2];
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-	struct tasklet_struct hfi_tasklet;
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+	bool initialized;
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+	bool hung;
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+	bool legacy; /* a618 or a630 */
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 };
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 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
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@@ -89,9 +97,11 @@
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 	return msm_writel(value, gmu->mmio + (offset << 2));
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 }
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-static inline void pdc_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
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+static inline void
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+gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
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 {
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-	return msm_writel(value, gmu->pdc_mmio + (offset << 2));
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+	memcpy_toio(gmu->mmio + (offset << 2), data, size);
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+	wmb();
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 }
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 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
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@@ -103,8 +113,32 @@
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 	gmu_write(gmu, reg, val | or);
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 }
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+static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
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+{
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+	u64 val;
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+
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+	val = (u64) msm_readl(gmu->mmio + (lo << 2));
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+	val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
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+
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+	return val;
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+}
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+
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 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
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 	readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
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+		interval, timeout)
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+
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+static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
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+{
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+	return msm_readl(gmu->rscc + (offset << 2));
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+}
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+
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+static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
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+{
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+	return msm_writel(value, gmu->rscc + (offset << 2));
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+}
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+
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+#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
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+	readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
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 		interval, timeout)
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 /*
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@@ -122,6 +156,7 @@
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 	GMU_OOB_BOOT_SLUMBER = 0,
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 	GMU_OOB_GPU_SET,
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 	GMU_OOB_DCVS_SET,
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+	GMU_OOB_PERFCOUNTER_SET,
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 };
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 /* These are the interrupt / ack bits for each OOB request that are set
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@@ -152,11 +187,25 @@
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 #define GMU_OOB_GPU_SET_ACK	24
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 #define GMU_OOB_GPU_SET_CLEAR	24
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+#define GMU_OOB_GPU_SET_REQUEST_NEW	30
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+#define GMU_OOB_GPU_SET_ACK_NEW		31
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+#define GMU_OOB_GPU_SET_CLEAR_NEW	31
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+
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+#define GMU_OOB_PERFCOUNTER_REQUEST	17
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+#define GMU_OOB_PERFCOUNTER_ACK		25
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+#define GMU_OOB_PERFCOUNTER_CLEAR	25
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+
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+#define GMU_OOB_PERFCOUNTER_REQUEST_NEW	28
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+#define GMU_OOB_PERFCOUNTER_ACK_NEW	30
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+#define GMU_OOB_PERFCOUNTER_CLEAR_NEW	30
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 void a6xx_hfi_init(struct a6xx_gmu *gmu);
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 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
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 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
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+int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
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+int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
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-void a6xx_hfi_task(unsigned long data);
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+bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
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+bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
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 #endif