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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/drivers/gpu/drm/msm/adreno/a3xx.xml.h
....@@ -8,19 +8,21 @@
88 git clone https://github.com/freedreno/envytools.git
99 
1010 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
13
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
15
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-06 18:45:45)
16
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-06 18:45:45)
19
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 101627 bytes, from 2018-08-06 18:45:45)
20
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
22
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
23
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
2224 
23
-Copyright (C) 2013-2018 by the following authors:
25
+Copyright (C) 2013-2020 by the following authors:
2426 - Rob Clark <robdclark@gmail.com> (robclark)
2527 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2628 
....@@ -48,7 +50,9 @@
4850 
4951 enum a3xx_tile_mode {
5052 	LINEAR = 0,
53
+	TILE_4X4 = 1,
5154 	TILE_32X32 = 2,
55
+	TILE_4X2 = 3,
5256 };
5357 
5458 enum a3xx_state_block_id {
....@@ -123,6 +127,7 @@
123127 	VFMT_2_10_10_10_UNORM = 61,
124128 	VFMT_2_10_10_10_SINT = 62,
125129 	VFMT_2_10_10_10_SNORM = 63,
130
+	VFMT_NONE = 255,
126131 };
127132 
128133 enum a3xx_tex_fmt {
....@@ -206,15 +211,7 @@
206211 	TFMT_ETC2_RGBA8 = 116,
207212 	TFMT_ETC2_RGB8A1 = 117,
208213 	TFMT_ETC2_RGB8 = 118,
209
-};
210
-
211
-enum a3xx_tex_fetchsize {
212
-	TFETCH_DISABLE = 0,
213
-	TFETCH_1_BYTE = 1,
214
-	TFETCH_2_BYTE = 2,
215
-	TFETCH_4_BYTE = 3,
216
-	TFETCH_8_BYTE = 4,
217
-	TFETCH_16_BYTE = 5,
214
+	TFMT_NONE = 255,
218215 };
219216 
220217 enum a3xx_color_fmt {
....@@ -228,8 +225,8 @@
228225 	RB_R8G8B8A8_SINT = 11,
229226 	RB_R8G8_UNORM = 12,
230227 	RB_R8G8_SNORM = 13,
231
-	RB_R8_UINT = 14,
232
-	RB_R8_SINT = 15,
228
+	RB_R8G8_UINT = 14,
229
+	RB_R8G8_SINT = 15,
233230 	RB_R10G10B10A2_UNORM = 16,
234231 	RB_A2R10G10B10_UNORM = 17,
235232 	RB_R10G10B10A2_UINT = 18,
....@@ -261,6 +258,7 @@
261258 	RB_R32_UINT = 56,
262259 	RB_R32G32_UINT = 57,
263260 	RB_R32G32B32A32_UINT = 59,
261
+	RB_NONE = 255,
264262 };
265263 
266264 enum a3xx_cp_perfcounter_select {
....@@ -932,6 +930,9 @@
932930 
933931 #define REG_A3XX_GRAS_CL_CLIP_CNTL				0x00002040
934932 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER			0x00001000
933
+#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER		0x00002000
934
+#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID		0x00004000
935
+#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID		0x00008000
935936 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
936937 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000
937938 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE		0x00080000
....@@ -1170,10 +1171,12 @@
11701171 }
11711172 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE		0x00001000
11721173 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM			0x00002000
1173
-#define A3XX_RB_RENDER_CONTROL_XCOORD				0x00004000
1174
-#define A3XX_RB_RENDER_CONTROL_YCOORD				0x00008000
1175
-#define A3XX_RB_RENDER_CONTROL_ZCOORD				0x00010000
1176
-#define A3XX_RB_RENDER_CONTROL_WCOORD				0x00020000
1174
+#define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK			0x0003c000
1175
+#define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT		14
1176
+static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val)
1177
+{
1178
+	return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK;
1179
+}
11771180 #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE			0x00080000
11781181 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE		0x00100000
11791182 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST			0x00400000
....@@ -1755,11 +1758,29 @@
17551758 }
17561759 
17571760 #define REG_A3XX_HLSQ_CONTROL_3_REG				0x00002203
1758
-#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK			0x000000ff
1759
-#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT			0
1760
-static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1761
+#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK	0x000000ff
1762
+#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT	0
1763
+static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val)
17611764 {
1762
-	return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1765
+	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK;
1766
+}
1767
+#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK	0x0000ff00
1768
+#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT	8
1769
+static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val)
1770
+{
1771
+	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK;
1772
+}
1773
+#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK	0x00ff0000
1774
+#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT	16
1775
+static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val)
1776
+{
1777
+	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK;
1778
+}
1779
+#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK	0xff000000
1780
+#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT	24
1781
+static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val)
1782
+{
1783
+	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK;
17631784 }
17641785 
17651786 #define REG_A3XX_HLSQ_VS_CONTROL_REG				0x00002204
....@@ -1941,8 +1962,6 @@
19411962 #define REG_A3XX_VFD_INDEX_MAX					0x00002243
19421963 
19431964 #define REG_A3XX_VFD_INSTANCEID_OFFSET				0x00002244
1944
-
1945
-#define REG_A3XX_VFD_INDEX_OFFSET				0x00002245
19461965 
19471966 #define REG_A3XX_VFD_INDEX_OFFSET				0x00002245
19481967 
....@@ -3107,7 +3126,12 @@
31073126 }
31083127 
31093128 #define REG_A3XX_TEX_CONST_0					0x00000000
3110
-#define A3XX_TEX_CONST_0_TILED					0x00000001
3129
+#define A3XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
3130
+#define A3XX_TEX_CONST_0_TILE_MODE__SHIFT			0
3131
+static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
3132
+{
3133
+	return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK;
3134
+}
31113135 #define A3XX_TEX_CONST_0_SRGB					0x00000004
31123136 #define A3XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
31133137 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT				4
....@@ -3172,11 +3196,11 @@
31723196 {
31733197 	return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
31743198 }
3175
-#define A3XX_TEX_CONST_1_FETCHSIZE__MASK			0xf0000000
3176
-#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT			28
3177
-static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
3199
+#define A3XX_TEX_CONST_1_PITCHALIGN__MASK			0xf0000000
3200
+#define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT			28
3201
+static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val)
31783202 {
3179
-	return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
3203
+	return ((val) << A3XX_TEX_CONST_1_PITCHALIGN__SHIFT) & A3XX_TEX_CONST_1_PITCHALIGN__MASK;
31803204 }
31813205 
31823206 #define REG_A3XX_TEX_CONST_2					0x00000002