change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/gpu/drm/meson/meson_viu.h
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@@ -1,19 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Copyright (C) 2016 BayLibre, SAS
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  * Author: Neil Armstrong <narmstrong@baylibre.com>
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of the
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- * License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, see <http://www.gnu.org/licenses/>.
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  */
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 /* Video Input Unit */
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@@ -22,6 +10,8 @@
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 #define __MESON_VIU_H
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11
 
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 /* OSDx_BLKx_CFG */
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+#define OSD_MALI_SRC_EN		BIT(30)
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+
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 #define OSD_CANVAS_SEL		16
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16
 
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 #define OSD_ENDIANNESS_LE	BIT(15)
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@@ -45,20 +35,38 @@
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 #define OSD_COLOR_MATRIX_16_RGB655	(0x00 << 2)
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 #define OSD_COLOR_MATRIX_16_RGB565	(0x04 << 2)
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+#define OSD_MALI_COLOR_MODE_R8		(0 << 8)
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+#define OSD_MALI_COLOR_MODE_YUV422	(1 << 8)
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+#define OSD_MALI_COLOR_MODE_RGB565	(2 << 8)
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+#define OSD_MALI_COLOR_MODE_RGBA5551	(3 << 8)
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+#define OSD_MALI_COLOR_MODE_RGBA4444	(4 << 8)
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+#define OSD_MALI_COLOR_MODE_RGBA8888	(5 << 8)
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+#define OSD_MALI_COLOR_MODE_RGB888	(7 << 8)
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+#define OSD_MALI_COLOR_MODE_YUV422_10B	(8 << 8)
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+#define OSD_MALI_COLOR_MODE_RGBA1010102	(9 << 8)
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+
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 #define OSD_INTERLACE_ENABLED	BIT(1)
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 #define OSD_INTERLACE_ODD	BIT(0)
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 #define OSD_INTERLACE_EVEN	(0)
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 /* OSDx_CTRL_STAT */
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 #define OSD_ENABLE		BIT(21)
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+#define OSD_MEM_LINEAR_ADDR	BIT(2)
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 #define OSD_BLK0_ENABLE		BIT(0)
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 #define OSD_GLOBAL_ALPHA_SHIFT	12
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 /* OSDx_CTRL_STAT2 */
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+#define OSD_DPATH_MALI_AFBCD	BIT(15)
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 #define OSD_REPLACE_EN		BIT(14)
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 #define OSD_REPLACE_SHIFT	6
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+#define OSD_PENDING_STAT_CLEAN	BIT(1)
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64
 
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+void meson_viu_osd1_reset(struct meson_drm *priv);
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+void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv);
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+void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv);
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+void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv);
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+void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv);
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 void meson_viu_init(struct meson_drm *priv);
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 #endif /* __MESON_VIU_H */