forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/drivers/gpu/drm/meson/meson_registers.h
....@@ -1,26 +1,18 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; either version 2 of the License, or
7
- * (at your option) any later version.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
144  */
155 
166 #ifndef __MESON_REGISTERS_H
177 #define __MESON_REGISTERS_H
188 
9
+#include <linux/io.h>
10
+
1911 /* Shift all registers by 2 */
2012 #define _REG(reg)	((reg) << 2)
2113 
2214 #define writel_bits_relaxed(mask, val, addr) \
23
-	writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
15
+	writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr)
2416 
2517 /* vpp2 */
2618 #define VPP2_DUMMY_DATA 0x1900
....@@ -146,11 +138,30 @@
146138 #define VIU_ADDR_START 0x1a00
147139 #define VIU_ADDR_END 0x1aff
148140 #define VIU_SW_RESET 0x1a01
141
+#define		VIU_SW_RESET_OSD1_AFBCD		BIT(31)
142
+#define		VIU_SW_RESET_G12A_OSD1_AFBCD	BIT(21)
143
+#define		VIU_SW_RESET_G12A_AFBC_ARB	BIT(19)
144
+#define		VIU_SW_RESET_OSD1               BIT(0)
149145 #define VIU_MISC_CTRL0 0x1a06
146
+#define		VIU_CTRL0_VD1_AFBC_MASK         0x170000
147
+#define		VIU_CTRL0_AFBC_TO_VD1		BIT(20)
150148 #define VIU_MISC_CTRL1 0x1a07
149
+#define		MALI_AFBC_MISC			GENMASK(15, 8)
151150 #define D2D3_INTF_LENGTH 0x1a08
152151 #define D2D3_INTF_CTRL0 0x1a09
152
+#define VD1_AFBCD0_MISC_CTRL 0x1a0a
153
+#define		VD1_AXI_SEL_AFBC		(1 << 12)
154
+#define		AFBC_VD1_SEL			(1 << 10)
155
+#define VD2_AFBCD1_MISC_CTRL 0x1a0b
153156 #define VIU_OSD1_CTRL_STAT 0x1a10
157
+#define		VIU_OSD1_OSD_BLK_ENABLE         BIT(0)
158
+#define		VIU_OSD1_OSD_MEM_MODE_LINEAR	BIT(2)
159
+#define		VIU_OSD1_POSTBLD_SRC_VD1        (1 << 8)
160
+#define		VIU_OSD1_POSTBLD_SRC_VD2        (2 << 8)
161
+#define		VIU_OSD1_POSTBLD_SRC_OSD1       (3 << 8)
162
+#define		VIU_OSD1_POSTBLD_SRC_OSD2       (4 << 8)
163
+#define		VIU_OSD1_OSD_ENABLE             BIT(21)
164
+#define		VIU_OSD1_CFG_SYN_EN             BIT(31)
154165 #define VIU_OSD1_CTRL_STAT2 0x1a2d
155166 #define VIU_OSD1_COLOR_ADDR 0x1a11
156167 #define VIU_OSD1_COLOR 0x1a12
....@@ -181,6 +192,16 @@
181192 #define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b
182193 #define VIU_OSD1_TEST_RDDATA 0x1a2c
183194 #define VIU_OSD1_PROT_CTRL 0x1a2e
195
+#define VIU_OSD1_MALI_UNPACK_CTRL 0x1a2f
196
+#define		VIU_OSD1_MALI_UNPACK_EN		BIT(31)
197
+#define		VIU_OSD1_MALI_AFBCD_R_REORDER	GENMASK(15, 12)
198
+#define		VIU_OSD1_MALI_AFBCD_G_REORDER	GENMASK(11, 8)
199
+#define		VIU_OSD1_MALI_AFBCD_B_REORDER	GENMASK(7, 4)
200
+#define		VIU_OSD1_MALI_AFBCD_A_REORDER	GENMASK(3, 0)
201
+#define		VIU_OSD1_MALI_REORDER_R		1
202
+#define		VIU_OSD1_MALI_REORDER_G		2
203
+#define		VIU_OSD1_MALI_REORDER_B		3
204
+#define		VIU_OSD1_MALI_REORDER_A		4
184205 #define VIU_OSD2_CTRL_STAT 0x1a30
185206 #define VIU_OSD2_CTRL_STAT2 0x1a4d
186207 #define VIU_OSD2_COLOR_ADDR 0x1a31
....@@ -216,6 +237,41 @@
216237 #define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b
217238 #define VIU_OSD2_TEST_RDDATA 0x1a4c
218239 #define VIU_OSD2_PROT_CTRL 0x1a4e
240
+#define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd
241
+#define VIU_OSD2_DIMM_CTRL 0x1acf
242
+
243
+#define VIU_OSD3_CTRL_STAT 0x3d80
244
+#define VIU_OSD3_CTRL_STAT2 0x3d81
245
+#define VIU_OSD3_COLOR_ADDR 0x3d82
246
+#define VIU_OSD3_COLOR 0x3d83
247
+#define VIU_OSD3_TCOLOR_AG0 0x3d84
248
+#define VIU_OSD3_TCOLOR_AG1 0x3d85
249
+#define VIU_OSD3_TCOLOR_AG2 0x3d86
250
+#define VIU_OSD3_TCOLOR_AG3 0x3d87
251
+#define VIU_OSD3_BLK0_CFG_W0 0x3d88
252
+#define VIU_OSD3_BLK0_CFG_W1 0x3d8c
253
+#define VIU_OSD3_BLK0_CFG_W2 0x3d90
254
+#define VIU_OSD3_BLK0_CFG_W3 0x3d94
255
+#define VIU_OSD3_BLK0_CFG_W4 0x3d98
256
+#define VIU_OSD3_BLK1_CFG_W4 0x3d99
257
+#define VIU_OSD3_BLK2_CFG_W4 0x3d9a
258
+#define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c
259
+#define VIU_OSD3_TEST_RDDATA 0x3d9d
260
+#define VIU_OSD3_PROT_CTRL 0x3d9e
261
+#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f
262
+#define VIU_OSD3_DIMM_CTRL 0x3da0
263
+
264
+#define VIU_OSD_DDR_PRIORITY_URGENT      BIT(0)
265
+#define VIU_OSD_HOLD_FIFO_LINES(lines)   ((lines & 0x1f) << 5)
266
+#define VIU_OSD_FIFO_DEPTH_VAL(val)      ((val & 0x7f) << 12)
267
+#define VIU_OSD_WORDS_PER_BURST(words)   (((words & 0x4) >> 1) << 22)
268
+#define VIU_OSD_FIFO_LIMITS(size)        ((size & 0xf) << 24)
269
+#define VIU_OSD_BURST_LENGTH_24          (0x0 << 31 | 0x0 << 10)
270
+#define VIU_OSD_BURST_LENGTH_32          (0x0 << 31 | 0x1 << 10)
271
+#define VIU_OSD_BURST_LENGTH_48          (0x0 << 31 | 0x2 << 10)
272
+#define VIU_OSD_BURST_LENGTH_64          (0x0 << 31 | 0x3 << 10)
273
+#define VIU_OSD_BURST_LENGTH_96          (0x1 << 31 | 0x0 << 10)
274
+#define VIU_OSD_BURST_LENGTH_128         (0x1 << 31 | 0x1 << 10)
219275 
220276 #define VD1_IF0_GEN_REG 0x1a50
221277 #define VD1_IF0_CANVAS0 0x1a51
....@@ -286,6 +342,28 @@
286342 #define VIU_OSD1_MATRIX_COEF22_30 0x1a9d
287343 #define VIU_OSD1_MATRIX_COEF31_32 0x1a9e
288344 #define VIU_OSD1_MATRIX_COEF40_41 0x1a9f
345
+#define VD1_IF0_GEN_REG3 0x1aa7
346
+
347
+#define VIU_OSD_BLENDO_H_START_END 0x1aa9
348
+#define VIU_OSD_BLENDO_V_START_END 0x1aaa
349
+#define VIU_OSD_BLEND_GEN_CTRL0 0x1aab
350
+#define VIU_OSD_BLEND_GEN_CTRL1 0x1aac
351
+#define VIU_OSD_BLEND_DUMMY_DATA 0x1aad
352
+#define VIU_OSD_BLEND_CURRENT_XY 0x1aae
353
+
354
+#define VIU_OSD2_MATRIX_CTRL 0x1ab0
355
+#define VIU_OSD2_MATRIX_COEF00_01 0x1ab1
356
+#define VIU_OSD2_MATRIX_COEF02_10 0x1ab2
357
+#define VIU_OSD2_MATRIX_COEF11_12 0x1ab3
358
+#define VIU_OSD2_MATRIX_COEF20_21 0x1ab4
359
+#define VIU_OSD2_MATRIX_COEF22 0x1ab5
360
+#define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6
361
+#define VIU_OSD2_MATRIX_OFFSET2 0x1ab7
362
+#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8
363
+#define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9
364
+#define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba
365
+#define VIU_OSD2_MATRIX_HL_COLOR 0x1abb
366
+#define VIU_OSD2_MATRIX_PROBE_POS 0x1abc
289367 #define VIU_OSD1_EOTF_CTL 0x1ad4
290368 #define VIU_OSD1_EOTF_COEF00_01 0x1ad5
291369 #define VIU_OSD1_EOTF_COEF02_10 0x1ad6
....@@ -297,12 +375,31 @@
297375 #define VIU_OSD1_OETF_CTL 0x1adc
298376 #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
299377 #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
378
+#define AFBC_ENABLE 0x1ae0
379
+#define AFBC_MODE 0x1ae1
380
+#define AFBC_SIZE_IN 0x1ae2
381
+#define AFBC_DEC_DEF_COLOR 0x1ae3
382
+#define AFBC_CONV_CTRL 0x1ae4
383
+#define AFBC_LBUF_DEPTH 0x1ae5
384
+#define AFBC_HEAD_BADDR 0x1ae6
385
+#define AFBC_BODY_BADDR 0x1ae7
386
+#define AFBC_SIZE_OUT 0x1ae8
387
+#define AFBC_OUT_YSCOPE 0x1ae9
388
+#define AFBC_STAT 0x1aea
389
+#define AFBC_VD_CFMT_CTRL 0x1aeb
390
+#define AFBC_VD_CFMT_W 0x1aec
391
+#define AFBC_MIF_HOR_SCOPE 0x1aed
392
+#define AFBC_MIF_VER_SCOPE 0x1aee
393
+#define AFBC_PIXEL_HOR_SCOPE 0x1aef
394
+#define AFBC_PIXEL_VER_SCOPE 0x1af0
395
+#define AFBC_VD_CFMT_H 0x1af1
300396 
301397 /* vpp */
302398 #define VPP_DUMMY_DATA 0x1d00
303399 #define VPP_LINE_IN_LENGTH 0x1d01
304400 #define VPP_PIC_IN_HEIGHT 0x1d02
305401 #define VPP_SCALE_COEF_IDX 0x1d03
402
+#define		VPP_SCALE_HORIZONTAL_COEF       BIT(8)
306403 #define VPP_SCALE_COEF 0x1d04
307404 #define VPP_VSC_REGION12_STARTP 0x1d05
308405 #define VPP_VSC_REGION34_STARTP 0x1d06
....@@ -324,6 +421,12 @@
324421 #define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17
325422 #define VPP_HSC_PHASE_CTRL 0x1d18
326423 #define VPP_SC_MISC 0x1d19
424
+#define		VPP_SC_VD_EN_ENABLE             BIT(15)
425
+#define		VPP_SC_TOP_EN_ENABLE            BIT(16)
426
+#define		VPP_SC_HSC_EN_ENABLE            BIT(17)
427
+#define		VPP_SC_VSC_EN_ENABLE            BIT(18)
428
+#define		VPP_VSC_BANK_LENGTH(length)     (length & 0x7)
429
+#define		VPP_HSC_BANK_LENGTH(length)     ((length & 0x7) << 8)
327430 #define VPP_PREBLEND_VD1_H_START_END 0x1d1a
328431 #define VPP_PREBLEND_VD1_V_START_END 0x1d1b
329432 #define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
....@@ -333,23 +436,28 @@
333436 #define VPP_PREBLEND_H_SIZE 0x1d20
334437 #define VPP_POSTBLEND_H_SIZE 0x1d21
335438 #define VPP_HOLD_LINES 0x1d22
439
+#define		VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf)
440
+#define		VPP_PREBLEND_HOLD_LINES(lines)  ((lines & 0xf) << 8)
336441 #define VPP_BLEND_ONECOLOR_CTRL 0x1d23
337442 #define VPP_PREBLEND_CURRENT_XY 0x1d24
338443 #define VPP_POSTBLEND_CURRENT_XY 0x1d25
339444 #define VPP_MISC 0x1d26
340
-#define		VPP_PREBLEND_ENABLE	BIT(6)
341
-#define		VPP_POSTBLEND_ENABLE	BIT(7)
342
-#define		VPP_OSD2_ALPHA_PREMULT	BIT(8)
343
-#define		VPP_OSD1_ALPHA_PREMULT	BIT(9)
344
-#define		VPP_VD1_POSTBLEND	BIT(10)
345
-#define		VPP_VD2_POSTBLEND	BIT(11)
346
-#define		VPP_OSD1_POSTBLEND	BIT(12)
347
-#define		VPP_OSD2_POSTBLEND	BIT(13)
348
-#define		VPP_VD1_PREBLEND	BIT(14)
349
-#define		VPP_VD2_PREBLEND	BIT(15)
350
-#define		VPP_OSD1_PREBLEND	BIT(16)
351
-#define		VPP_OSD2_PREBLEND	BIT(17)
445
+#define		VPP_PREBLEND_ENABLE             BIT(6)
446
+#define		VPP_POSTBLEND_ENABLE            BIT(7)
447
+#define		VPP_OSD2_ALPHA_PREMULT          BIT(8)
448
+#define		VPP_OSD1_ALPHA_PREMULT          BIT(9)
449
+#define		VPP_VD1_POSTBLEND               BIT(10)
450
+#define		VPP_VD2_POSTBLEND               BIT(11)
451
+#define		VPP_OSD1_POSTBLEND              BIT(12)
452
+#define		VPP_OSD2_POSTBLEND              BIT(13)
453
+#define		VPP_VD1_PREBLEND                BIT(14)
454
+#define		VPP_VD2_PREBLEND                BIT(15)
455
+#define		VPP_OSD1_PREBLEND               BIT(16)
456
+#define		VPP_OSD2_PREBLEND               BIT(17)
457
+#define		VPP_COLOR_MNG_ENABLE            BIT(28)
352458 #define VPP_OFIFO_SIZE 0x1d27
459
+#define		VPP_OFIFO_SIZE_MASK             GENMASK(13, 0)
460
+#define		VPP_OFIFO_SIZE_DEFAULT          (0xfff << 20 | 0x1000)
353461 #define VPP_FIFO_STATUS 0x1d28
354462 #define VPP_SMOKE_CTRL 0x1d29
355463 #define VPP_SMOKE1_VAL 0x1d2a
....@@ -365,6 +473,8 @@
365473 #define VPP_HSC_PHASE_CTRL1 0x1d34
366474 #define VPP_HSC_INI_PAT_CTRL 0x1d35
367475 #define VPP_VADJ_CTRL 0x1d40
476
+#define		VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1)
477
+
368478 #define VPP_VADJ1_Y 0x1d41
369479 #define VPP_VADJ1_MA_MB 0x1d42
370480 #define VPP_VADJ1_MC_MD 0x1d43
....@@ -424,6 +534,7 @@
424534 #define VPP_PEAKING_VGAIN 0x1d92
425535 #define VPP_PEAKING_NLP_1 0x1d93
426536 #define VPP_DOLBY_CTRL 0x1d93
537
+#define VPP_PPS_DUMMY_DATA_MODE (1 << 17)
427538 #define VPP_PEAKING_NLP_2 0x1d94
428539 #define VPP_PEAKING_NLP_3 0x1d95
429540 #define VPP_PEAKING_NLP_4 0x1d96
....@@ -477,6 +588,88 @@
477588 #define VPP_OSD_SCALE_COEF_IDX 0x1dcc
478589 #define VPP_OSD_SCALE_COEF 0x1dcd
479590 #define VPP_INT_LINE_NUM 0x1dce
591
+
592
+#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60
593
+#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61
594
+#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62
595
+#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63
596
+#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64
597
+#define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65
598
+#define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66
599
+#define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67
600
+#define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68
601
+#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69
602
+#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a
603
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b
604
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c
605
+#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
606
+
607
+#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70
608
+#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71
609
+#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72
610
+#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73
611
+#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74
612
+#define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75
613
+#define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76
614
+#define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77
615
+#define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78
616
+#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79
617
+#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a
618
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b
619
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c
620
+#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
621
+
622
+#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0
623
+#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1
624
+#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2
625
+#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3
626
+#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4
627
+#define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5
628
+#define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6
629
+#define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7
630
+#define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8
631
+#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9
632
+#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba
633
+#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb
634
+#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
635
+#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
636
+
637
+/* osd1 HDR */
638
+#define OSD1_HDR2_CTRL 0x38a0
639
+#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN       BIT(13)
640
+#define OSD1_HDR2_CTRL_REG_ONLY_MAT            BIT(16)
641
+
642
+/* osd2 scaler */
643
+#define OSD2_VSC_PHASE_STEP 0x3d00
644
+#define OSD2_VSC_INI_PHASE 0x3d01
645
+#define OSD2_VSC_CTRL0 0x3d02
646
+#define OSD2_HSC_PHASE_STEP 0x3d03
647
+#define OSD2_HSC_INI_PHASE 0x3d04
648
+#define OSD2_HSC_CTRL0 0x3d05
649
+#define OSD2_HSC_INI_PAT_CTRL 0x3d06
650
+#define OSD2_SC_DUMMY_DATA 0x3d07
651
+#define OSD2_SC_CTRL0 0x3d08
652
+#define OSD2_SCI_WH_M1 0x3d09
653
+#define OSD2_SCO_H_START_END 0x3d0a
654
+#define OSD2_SCO_V_START_END 0x3d0b
655
+#define OSD2_SCALE_COEF_IDX 0x3d18
656
+#define OSD2_SCALE_COEF 0x3d19
657
+
658
+/* osd34 scaler */
659
+#define OSD34_SCALE_COEF_IDX 0x3d1e
660
+#define OSD34_SCALE_COEF 0x3d1f
661
+#define OSD34_VSC_PHASE_STEP 0x3d20
662
+#define OSD34_VSC_INI_PHASE 0x3d21
663
+#define OSD34_VSC_CTRL0 0x3d22
664
+#define OSD34_HSC_PHASE_STEP 0x3d23
665
+#define OSD34_HSC_INI_PHASE 0x3d24
666
+#define OSD34_HSC_CTRL0 0x3d25
667
+#define OSD34_HSC_INI_PAT_CTRL 0x3d26
668
+#define OSD34_SC_DUMMY_DATA 0x3d27
669
+#define OSD34_SC_CTRL0 0x3d28
670
+#define OSD34_SCI_WH_M1 0x3d29
671
+#define OSD34_SCO_H_START_END 0x3d2a
672
+#define OSD34_SCO_V_START_END 0x3d2b
480673 
481674 /* viu2 */
482675 #define VIU2_ADDR_START 0x1e00
....@@ -591,6 +784,25 @@
591784 #define VENC_UPSAMPLE_CTRL0 0x1b64
592785 #define VENC_UPSAMPLE_CTRL1 0x1b65
593786 #define VENC_UPSAMPLE_CTRL2 0x1b66
787
+#define		VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO        BIT(0)
788
+#define		VENC_UPSAMPLE_CTRL_F1_EN                 BIT(5)
789
+#define		VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN        BIT(6)
790
+#define		VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA   (0x0 << 12)
791
+#define		VENC_UPSAMPLE_CTRL_CVBS                  (0x1 << 12)
792
+#define		VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA          (0x2 << 12)
793
+#define		VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA        (0x3 << 12)
794
+#define		VENC_UPSAMPLE_CTRL_INTERLACE_PB          (0x4 << 12)
795
+#define		VENC_UPSAMPLE_CTRL_INTERLACE_PR          (0x5 << 12)
796
+#define		VENC_UPSAMPLE_CTRL_INTERLACE_R           (0x6 << 12)
797
+#define		VENC_UPSAMPLE_CTRL_INTERLACE_G           (0x7 << 12)
798
+#define		VENC_UPSAMPLE_CTRL_INTERLACE_B           (0x8 << 12)
799
+#define		VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y         (0x9 << 12)
800
+#define		VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB        (0xa << 12)
801
+#define		VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR        (0xb << 12)
802
+#define		VENC_UPSAMPLE_CTRL_PROGRESSIVE_R         (0xc << 12)
803
+#define		VENC_UPSAMPLE_CTRL_PROGRESSIVE_G         (0xd << 12)
804
+#define		VENC_UPSAMPLE_CTRL_PROGRESSIVE_B         (0xe << 12)
805
+#define		VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE       (0xf << 12)
594806 #define TCON_INVERT_CTL 0x1b67
595807 #define VENC_VIDEO_PROG_MODE 0x1b68
596808 #define VENC_ENCI_LINE 0x1b69
....@@ -599,6 +811,7 @@
599811 #define VENC_ENCP_PIXEL 0x1b6c
600812 #define VENC_STATA 0x1b6d
601813 #define VENC_INTCTRL 0x1b6e
814
+#define		VENC_INTCTRL_ENCI_LNRST_INT_EN  BIT(1)
602815 #define VENC_INTFLAG 0x1b6f
603816 #define VENC_VIDEO_TST_EN 0x1b70
604817 #define VENC_VIDEO_TST_MDSEL 0x1b71
....@@ -609,6 +822,7 @@
609822 #define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76
610823 #define VENC_VIDEO_TST_VDCNT_STSET 0x1b77
611824 #define VENC_VDAC_DACSEL0 0x1b78
825
+#define		VENC_VDAC_SEL_ATV_DMD           BIT(5)
612826 #define VENC_VDAC_DACSEL1 0x1b79
613827 #define VENC_VDAC_DACSEL2 0x1b7a
614828 #define VENC_VDAC_DACSEL3 0x1b7b
....@@ -629,6 +843,7 @@
629843 #define VENC_VDAC_DAC5_GAINCTRL 0x1bfa
630844 #define VENC_VDAC_DAC5_OFFSET 0x1bfb
631845 #define VENC_VDAC_FIFO_CTRL 0x1bfc
846
+#define		VENC_VDAC_FIFO_EN_ENCI_ENABLE   BIT(13)
632847 #define ENCL_TCON_INVERT_CTL 0x1bfd
633848 #define ENCP_VIDEO_EN 0x1b80
634849 #define ENCP_VIDEO_SYNC_MODE 0x1b81
....@@ -644,6 +859,7 @@
644859 #define ENCP_VIDEO_SYNC_OFFST 0x1b8b
645860 #define ENCP_VIDEO_MACV_OFFST 0x1b8c
646861 #define ENCP_VIDEO_MODE 0x1b8d
862
+#define		ENCP_VIDEO_MODE_DE_V_HIGH       BIT(14)
647863 #define ENCP_VIDEO_MODE_ADV 0x1b8e
648864 #define ENCP_DBG_PX_RST 0x1b90
649865 #define ENCP_DBG_LN_RST 0x1b91
....@@ -722,6 +938,11 @@
722938 #define C656_FS_LNED 0x1be7
723939 #define ENCI_VIDEO_MODE 0x1b00
724940 #define ENCI_VIDEO_MODE_ADV 0x1b01
941
+#define		ENCI_VIDEO_MODE_ADV_DMXMD(val)          (val & 0x3)
942
+#define		ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22   BIT(2)
943
+#define		ENCI_VIDEO_MODE_ADV_YBW_MEDIUM          (0 << 4)
944
+#define		ENCI_VIDEO_MODE_ADV_YBW_LOW             (0x1 << 4)
945
+#define		ENCI_VIDEO_MODE_ADV_YBW_HIGH            (0x2 << 4)
725946 #define ENCI_VIDEO_FSC_ADJ 0x1b02
726947 #define ENCI_VIDEO_BRIGHT 0x1b03
727948 #define ENCI_VIDEO_CONT 0x1b04
....@@ -792,13 +1013,17 @@
7921013 #define ENCI_DBG_MAXPX 0x1b4c
7931014 #define ENCI_DBG_MAXLN 0x1b4d
7941015 #define ENCI_MACV_MAX_AMP 0x1b50
1016
+#define		ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15)
1017
+#define		ENCI_MACV_MAX_AMP_VAL(val)      (val & 0x83ff)
7951018 #define ENCI_MACV_PULSE_LO 0x1b51
7961019 #define ENCI_MACV_PULSE_HI 0x1b52
7971020 #define ENCI_MACV_BKP_MAX 0x1b53
7981021 #define ENCI_CFILT_CTRL 0x1b54
1022
+#define		ENCI_CFILT_CMPT_SEL_HIGH        BIT(1)
7991023 #define ENCI_CFILT7 0x1b55
8001024 #define ENCI_YC_DELAY 0x1b56
8011025 #define ENCI_VIDEO_EN 0x1b57
1026
+#define		ENCI_VIDEO_EN_ENABLE            BIT(0)
8021027 #define ENCI_DVI_HSO_BEGIN 0x1c00
8031028 #define ENCI_DVI_HSO_END 0x1c01
8041029 #define ENCI_DVI_VSO_BLINE_EVN 0x1c02
....@@ -810,6 +1035,10 @@
8101035 #define ENCI_DVI_VSO_END_EVN 0x1c08
8111036 #define ENCI_DVI_VSO_END_ODD 0x1c09
8121037 #define ENCI_CFILT_CTRL2 0x1c0a
1038
+#define		ENCI_CFILT_CMPT_CR_DLY(delay)   (delay & 0xf)
1039
+#define		ENCI_CFILT_CMPT_CB_DLY(delay)   ((delay & 0xf) << 4)
1040
+#define		ENCI_CFILT_CVBS_CR_DLY(delay)   ((delay & 0xf) << 8)
1041
+#define		ENCI_CFILT_CVBS_CB_DLY(delay)   ((delay & 0xf) << 12)
8131042 #define ENCI_DACSEL_0 0x1c0b
8141043 #define ENCI_DACSEL_1 0x1c0c
8151044 #define ENCP_DACSEL_0 0x1c0d
....@@ -824,6 +1053,8 @@
8241053 #define ENCI_TST_CLRBAR_WIDTH 0x1c16
8251054 #define ENCI_TST_VDCNT_STSET 0x1c17
8261055 #define ENCI_VFIFO2VD_CTL 0x1c18
1056
+#define		ENCI_VFIFO2VD_CTL_ENABLE        BIT(0)
1057
+#define		ENCI_VFIFO2VD_CTL_VD_SEL(val)   ((val & 0xff) << 8)
8271058 #define ENCI_VFIFO2VD_PIXEL_START 0x1c19
8281059 #define ENCI_VFIFO2VD_PIXEL_END 0x1c1a
8291060 #define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
....@@ -886,6 +1117,7 @@
8861117 #define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56
8871118 #define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57
8881119 #define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58
1120
+#define		VENC_VDAC_DAC0_FILT_CTRL0_EN    BIT(0)
8891121 #define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59
8901122 #define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a
8911123 #define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b
....@@ -1012,11 +1244,59 @@
10121244 #define RDMA_AHB_START_ADDR_7 0x110e
10131245 #define RDMA_AHB_END_ADDR_7 0x110f
10141246 #define RDMA_ACCESS_AUTO 0x1110
1247
+#define		RDMA_ACCESS_TRIGGER_CHAN3	GENMASK(31, 24)
1248
+#define		RDMA_ACCESS_TRIGGER_CHAN2	GENMASK(23, 16)
1249
+#define		RDMA_ACCESS_TRIGGER_CHAN1	GENMASK(15, 8)
1250
+#define		RDMA_ACCESS_TRIGGER_STOP	0
1251
+#define		RDMA_ACCESS_TRIGGER_VSYNC	1
1252
+#define		RDMA_ACCESS_TRIGGER_LINE	32
1253
+#define		RDMA_ACCESS_RW_FLAG_CHAN3	BIT(7)
1254
+#define		RDMA_ACCESS_RW_FLAG_CHAN2	BIT(6)
1255
+#define		RDMA_ACCESS_RW_FLAG_CHAN1	BIT(5)
1256
+#define		RDMA_ACCESS_ADDR_INC_CHAN3	BIT(3)
1257
+#define		RDMA_ACCESS_ADDR_INC_CHAN2	BIT(2)
1258
+#define		RDMA_ACCESS_ADDR_INC_CHAN1	BIT(1)
10151259 #define RDMA_ACCESS_AUTO2 0x1111
1260
+#define		RDMA_ACCESS_RW_FLAG_CHAN7	BIT(7)
1261
+#define		RDMA_ACCESS_RW_FLAG_CHAN6	BIT(6)
1262
+#define		RDMA_ACCESS_RW_FLAG_CHAN5	BIT(5)
1263
+#define		RDMA_ACCESS_RW_FLAG_CHAN4	BIT(4)
1264
+#define		RDMA_ACCESS_ADDR_INC_CHAN7	BIT(3)
1265
+#define		RDMA_ACCESS_ADDR_INC_CHAN6	BIT(2)
1266
+#define		RDMA_ACCESS_ADDR_INC_CHAN5	BIT(1)
1267
+#define		RDMA_ACCESS_ADDR_INC_CHAN4	BIT(0)
10161268 #define RDMA_ACCESS_AUTO3 0x1112
1269
+#define		RDMA_ACCESS_TRIGGER_CHAN7	GENMASK(31, 24)
1270
+#define		RDMA_ACCESS_TRIGGER_CHAN6	GENMASK(23, 16)
1271
+#define		RDMA_ACCESS_TRIGGER_CHAN5	GENMASK(15, 8)
1272
+#define		RDMA_ACCESS_TRIGGER_CHAN4	GENMASK(7, 0)
10171273 #define RDMA_ACCESS_MAN 0x1113
1274
+#define		RDMA_ACCESS_MAN_RW_FLAG		BIT(2)
1275
+#define		RDMA_ACCESS_MAN_ADDR_INC	BIT(1)
1276
+#define		RDMA_ACCESS_MAN_START		BIT(0)
10181277 #define RDMA_CTRL 0x1114
1278
+#define		RDMA_IRQ_CLEAR_CHAN7	BIT(31)
1279
+#define		RDMA_IRQ_CLEAR_CHAN6	BIT(30)
1280
+#define		RDMA_IRQ_CLEAR_CHAN5	BIT(29)
1281
+#define		RDMA_IRQ_CLEAR_CHAN4	BIT(28)
1282
+#define		RDMA_IRQ_CLEAR_CHAN3	BIT(27)
1283
+#define		RDMA_IRQ_CLEAR_CHAN2	BIT(26)
1284
+#define		RDMA_IRQ_CLEAR_CHAN1	BIT(25)
1285
+#define		RDMA_IRQ_CLEAR_CHAN_MAN	BIT(24)
1286
+#define		RDMA_DEFAULT_CONFIG	(BIT(7) | BIT(6))
1287
+#define		RDMA_CTRL_AHB_WR_BURST	GENMASK(5, 4)
1288
+#define		RDMA_CTRL_AHB_RD_BURST	GENMASK(3, 2)
1289
+#define		RDMA_CTRL_SW_RESET	BIT(1)
1290
+#define		RDMA_CTRL_FREE_CLK_EN	BIT(0)
10191291 #define RDMA_STATUS 0x1115
1292
+#define		RDMA_IRQ_STAT_CHAN7	BIT(31)
1293
+#define		RDMA_IRQ_STAT_CHAN6	BIT(30)
1294
+#define		RDMA_IRQ_STAT_CHAN5	BIT(29)
1295
+#define		RDMA_IRQ_STAT_CHAN4	BIT(28)
1296
+#define		RDMA_IRQ_STAT_CHAN3	BIT(27)
1297
+#define		RDMA_IRQ_STAT_CHAN2	BIT(26)
1298
+#define		RDMA_IRQ_STAT_CHAN1	BIT(25)
1299
+#define		RDMA_IRQ_STAT_CHAN_MAN	BIT(24)
10201300 #define RDMA_STATUS2 0x1116
10211301 #define RDMA_STATUS3 0x1117
10221302 #define L_GAMMA_CNTL_PORT 0x1400
....@@ -1291,6 +1571,18 @@
12911571 #define		VIU2_SEL_VENC_ENCP	(2 << 2)
12921572 #define		VIU2_SEL_VENC_ENCT	(3 << 2)
12931573 #define VPU_HDMI_SETTING 0x271b
1574
+#define		VPU_HDMI_ENCI_DATA_TO_HDMI      BIT(0)
1575
+#define		VPU_HDMI_ENCP_DATA_TO_HDMI      BIT(1)
1576
+#define		VPU_HDMI_INV_HSYNC              BIT(2)
1577
+#define		VPU_HDMI_INV_VSYNC              BIT(3)
1578
+#define		VPU_HDMI_OUTPUT_CRYCB           (0 << 5)
1579
+#define		VPU_HDMI_OUTPUT_YCBCR           (1 << 5)
1580
+#define		VPU_HDMI_OUTPUT_YCRCB           (2 << 5)
1581
+#define		VPU_HDMI_OUTPUT_CBCRY           (3 << 5)
1582
+#define		VPU_HDMI_OUTPUT_CBYCR           (4 << 5)
1583
+#define		VPU_HDMI_OUTPUT_CRCBY           (5 << 5)
1584
+#define		VPU_HDMI_WR_RATE(rate)          (((rate & 0x1f) - 1) << 8)
1585
+#define		VPU_HDMI_RD_RATE(rate)          (((rate & 0x1f) - 1) << 12)
12941586 #define ENCI_INFO_READ 0x271c
12951587 #define ENCP_INFO_READ 0x271d
12961588 #define ENCT_INFO_READ 0x271e
....@@ -1367,6 +1659,7 @@
13671659 #define VPU_RDARB_MODE_L1C2 0x2799
13681660 #define VPU_RDARB_MODE_L2C1 0x279d
13691661 #define VPU_WRARB_MODE_L2C1 0x27a2
1662
+#define		VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc))
13701663 
13711664 /* osd super scale */
13721665 #define OSDSR_HV_SIZEIN 0x3130
....@@ -1397,4 +1690,196 @@
13971690 #define OSDSR_YBIC_VCOEF0 0x3149
13981691 #define OSDSR_CBIC_VCOEF0 0x314a
13991692 
1693
+/* osd afbcd on gxtvbb */
1694
+#define OSD1_AFBCD_ENABLE 0x31a0
1695
+#define		OSD1_AFBCD_ID_FIFO_THRD			GENMASK(15, 9)
1696
+#define		OSD1_AFBCD_DEC_ENABLE			BIT(8)
1697
+#define		OSD1_AFBCD_FRM_START			BIT(0)
1698
+#define OSD1_AFBCD_MODE 0x31a1
1699
+#define		OSD1_AFBCD_SOFT_RESET			BIT(31)
1700
+#define		OSD1_AFBCD_AXI_REORDER_MODE		BIT(28)
1701
+#define		OSD1_AFBCD_MIF_URGENT			GENMASK(25, 24)
1702
+#define		OSD1_AFBCD_HOLD_LINE_NUM		GENMASK(22, 16)
1703
+#define		OSD1_AFBCD_RGBA_EXCHAN_CTRL		GENMASK(15, 8)
1704
+#define		OSD1_AFBCD_HREG_BLOCK_SPLIT		BIT(6)
1705
+#define		OSD1_AFBCD_HREG_HALF_BLOCK		BIT(5)
1706
+#define		OSD1_AFBCD_HREG_PIXEL_PACKING_FMT	GENMASK(4, 0)
1707
+#define OSD1_AFBCD_SIZE_IN 0x31a2
1708
+#define		OSD1_AFBCD_HREG_VSIZE_IN		GENMASK(31, 16)
1709
+#define		OSD1_AFBCD_HREG_HSIZE_IN		GENMASK(15, 0)
1710
+#define OSD1_AFBCD_HDR_PTR 0x31a3
1711
+#define OSD1_AFBCD_FRAME_PTR 0x31a4
1712
+#define OSD1_AFBCD_CHROMA_PTR 0x31a5
1713
+#define OSD1_AFBCD_CONV_CTRL 0x31a6
1714
+#define		OSD1_AFBCD_CONV_LBUF_LEN		GENMASK(15, 0)
1715
+#define OSD1_AFBCD_STATUS 0x31a8
1716
+#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9
1717
+#define		OSD1_AFBCD_DEC_PIXEL_BGN_H		GENMASK(31, 16)
1718
+#define		OSD1_AFBCD_DEC_PIXEL_END_H		GENMASK(15, 0)
1719
+#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa
1720
+#define		OSD1_AFBCD_DEC_PIXEL_BGN_V		GENMASK(31, 16)
1721
+#define		OSD1_AFBCD_DEC_PIXEL_END_V		GENMASK(15, 0)
1722
+
1723
+/* add for gxm and 962e dv core2 */
1724
+#define DOLBY_CORE2A_SWAP_CTRL1	0x3434
1725
+#define DOLBY_CORE2A_SWAP_CTRL2	0x3435
1726
+
1727
+/* osd afbc on g12a */
1728
+#define VPU_MAFBC_BLOCK_ID 0x3a00
1729
+#define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01
1730
+#define VPU_MAFBC_IRQ_CLEAR 0x3a02
1731
+#define VPU_MAFBC_IRQ_MASK 0x3a03
1732
+#define VPU_MAFBC_IRQ_STATUS 0x3a04
1733
+#define		VPU_MAFBC_IRQ_SECURE_ID_ERROR		BIT(5)
1734
+#define		VPU_MAFBC_IRQ_AXI_ERROR			BIT(4)
1735
+#define		VPU_MAFBC_IRQ_DETILING_ERROR		BIT(3)
1736
+#define		VPU_MAFBC_IRQ_DECODE_ERROR		BIT(2)
1737
+#define		VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED	BIT(1)
1738
+#define		VPU_MAFBC_IRQ_SURFACES_COMPLETED	BIT(0)
1739
+#define VPU_MAFBC_COMMAND 0x3a05
1740
+#define		VPU_MAFBC_PENDING_SWAP	BIT(1)
1741
+#define		VPU_MAFBC_DIRECT_SWAP	BIT(0)
1742
+#define VPU_MAFBC_STATUS 0x3a06
1743
+#define		VPU_MAFBC_ERROR		BIT(2)
1744
+#define		VPU_MAFBC_SWAPPING	BIT(1)
1745
+#define		VPU_MAFBC_ACTIVE	BIT(0)
1746
+#define VPU_MAFBC_SURFACE_CFG 0x3a07
1747
+#define		VPU_MAFBC_CONTINUOUS_DECODING_ENABLE	BIT(16)
1748
+#define		VPU_MAFBC_S3_ENABLE			BIT(3)
1749
+#define		VPU_MAFBC_S2_ENABLE			BIT(2)
1750
+#define		VPU_MAFBC_S1_ENABLE			BIT(1)
1751
+#define		VPU_MAFBC_S0_ENABLE			BIT(0)
1752
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10
1753
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11
1754
+#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
1755
+#define		VPU_MAFBC_PAYLOAD_LIMIT_EN	BIT(19)
1756
+#define		VPU_MAFBC_TILED_HEADER_EN	BIT(18)
1757
+#define		VPU_MAFBC_SUPER_BLOCK_ASPECT	GENMASK(17, 16)
1758
+#define		VPU_MAFBC_BLOCK_SPLIT		BIT(9)
1759
+#define		VPU_MAFBC_YUV_TRANSFORM		BIT(8)
1760
+#define		VPU_MAFBC_PIXEL_FORMAT		GENMASK(3, 0)
1761
+#define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13
1762
+#define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14
1763
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15
1764
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16
1765
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17
1766
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18
1767
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19
1768
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a
1769
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b
1770
+#define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c
1771
+#define		VPU_MAFBC_PREFETCH_READ_DIRECTION_Y	BIT(1)
1772
+#define		VPU_MAFBC_PREFETCH_READ_DIRECTION_X	BIT(0)
1773
+
1774
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30
1775
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31
1776
+#define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32
1777
+#define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33
1778
+#define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34
1779
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35
1780
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36
1781
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37
1782
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38
1783
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39
1784
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a
1785
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b
1786
+#define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c
1787
+
1788
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50
1789
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51
1790
+#define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52
1791
+#define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53
1792
+#define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54
1793
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55
1794
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56
1795
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57
1796
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58
1797
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59
1798
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a
1799
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b
1800
+#define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c
1801
+
1802
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70
1803
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71
1804
+#define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72
1805
+#define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73
1806
+#define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74
1807
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75
1808
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76
1809
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77
1810
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78
1811
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79
1812
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a
1813
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b
1814
+#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c
1815
+
1816
+#define DOLBY_PATH_CTRL 0x1a0c
1817
+#define		DOLBY_BYPASS_EN(val)            (val & 0xf)
1818
+#define OSD_PATH_MISC_CTRL 0x1a0e
1819
+#define		OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD	BIT(4)
1820
+#define		OSD_PATH_OSD_AXI_SEL_OSD2_AFBCD	BIT(5)
1821
+#define		OSD_PATH_OSD_AXI_SEL_OSD3_AFBCD	BIT(6)
1822
+#define MALI_AFBCD_TOP_CTRL 0x1a0f
1823
+#define		MALI_AFBCD_MANUAL_RESET		BIT(23)
1824
+
1825
+#define VIU_OSD_BLEND_CTRL 0x39b0
1826
+#define		VIU_OSD_BLEND_REORDER(dest, src)      ((src) << (dest * 4))
1827
+#define		VIU_OSD_BLEND_DIN_EN(bits)            ((bits & 0xf) << 20)
1828
+#define		VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1   BIT(24)
1829
+#define		VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2  BIT(25)
1830
+#define		VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0    BIT(26)
1831
+#define		VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27)
1832
+#define		VIU_OSD_BLEND_HOLD_LINES(lines)       ((lines & 0x7) << 29)
1833
+#define VIU_OSD_BLEND_CTRL1 0x39c0
1834
+#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1
1835
+#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2
1836
+#define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3
1837
+#define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4
1838
+#define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5
1839
+#define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6
1840
+#define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7
1841
+#define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8
1842
+#define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9
1843
+#define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba
1844
+#define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb
1845
+#define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc
1846
+#define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf
1847
+
1848
+#define VPP_OUT_H_V_SIZE 0x1da5
1849
+
1850
+#define VPP_VD2_HDR_IN_SIZE 0x1df0
1851
+#define VPP_OSD1_IN_SIZE 0x1df1
1852
+#define VPP_GCLK_CTRL2 0x1df2
1853
+#define VD2_PPS_DUMMY_DATA 0x1df4
1854
+#define VPP_OSD1_BLD_H_SCOPE 0x1df5
1855
+#define VPP_OSD1_BLD_V_SCOPE 0x1df6
1856
+#define VPP_OSD2_BLD_H_SCOPE 0x1df7
1857
+#define VPP_OSD2_BLD_V_SCOPE 0x1df8
1858
+#define VPP_WRBAK_CTRL 0x1df9
1859
+#define VPP_SLEEP_CTRL 0x1dfa
1860
+#define VD1_BLEND_SRC_CTRL 0x1dfb
1861
+#define VD2_BLEND_SRC_CTRL 0x1dfc
1862
+#define		VD_BLEND_PREBLD_SRC_VD1         (1 << 0)
1863
+#define		VD_BLEND_PREBLD_SRC_VD2         (2 << 0)
1864
+#define		VD_BLEND_PREBLD_SRC_OSD1        (3 << 0)
1865
+#define		VD_BLEND_PREBLD_SRC_OSD2        (4 << 0)
1866
+#define		VD_BLEND_PREBLD_PREMULT_EN      BIT(4)
1867
+#define		VD_BLEND_POSTBLD_SRC_VD1        (1 << 8)
1868
+#define		VD_BLEND_POSTBLD_SRC_VD2        (2 << 8)
1869
+#define		VD_BLEND_POSTBLD_SRC_OSD1       (3 << 8)
1870
+#define		VD_BLEND_POSTBLD_SRC_OSD2       (4 << 8)
1871
+#define		VD_BLEND_POSTBLD_PREMULT_EN     BIT(16)
1872
+#define OSD1_BLEND_SRC_CTRL 0x1dfd
1873
+#define OSD2_BLEND_SRC_CTRL 0x1dfe
1874
+#define		OSD_BLEND_POSTBLD_SRC_VD1       (1 << 8)
1875
+#define		OSD_BLEND_POSTBLD_SRC_VD2       (2 << 8)
1876
+#define		OSD_BLEND_POSTBLD_SRC_OSD1      (3 << 8)
1877
+#define		OSD_BLEND_POSTBLD_SRC_OSD2      (4 << 8)
1878
+#define		OSD_BLEND_PATH_SEL_ENABLE       BIT(20)
1879
+
1880
+#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968
1881
+#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969
1882
+#define VPP_RDARB_MODE 0x3978
1883
+#define VPP_RDARB_REQEN_SLV 0x3979
1884
+
14001885 #endif /* __MESON_REGISTERS_H */