~hc/RK356X_SDK_RELEASE.git

..	..	@@ -28,14 +28,29 @@
28	28
29	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30	30
31		-#include <linux/sysrq.h>
32		-#include <linux/slab.h>
33	31	#include <linux/circ_buf.h>
34		-#include <drm/drmP.h>
35		-#include <drm/i915_drm.h>
	32	+#include <linux/slab.h>
	33	+#include <linux/sysrq.h>
	34	+
	35	+#include <drm/drm_drv.h>
	36	+#include <drm/drm_irq.h>
	37	+
	38	+#include "display/intel_display_types.h"
	39	+#include "display/intel_fifo_underrun.h"
	40	+#include "display/intel_hotplug.h"
	41	+#include "display/intel_lpe_audio.h"
	42	+#include "display/intel_psr.h"
	43	+
	44	+#include "gt/intel_breadcrumbs.h"
	45	+#include "gt/intel_gt.h"
	46	+#include "gt/intel_gt_irq.h"
	47	+#include "gt/intel_gt_pm_irq.h"
	48	+#include "gt/intel_rps.h"
	49	+
36	50	#include "i915_drv.h"
	51	+#include "i915_irq.h"
37	52	#include "i915_trace.h"
38		-#include "intel_drv.h"
	53	+#include "intel_pm.h"
39	54
40	55	/**
41	56	* DOC: interrupt handling
..	..	@@ -44,6 +59,8 @@
44	59	* interrupt handling support. There's a lot more functionality in i915_irq.c
45	60	* and related files, but that will be described in separate chapters.
46	61	*/
	62	+
	63	+typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
47	64
48	65	static const u32 hpd_ilk[HPD_NUM_PINS] = {
49	66	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
..	..	@@ -62,7 +79,7 @@
62	79	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63	80	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64	81	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65		- [HPD_PORT_D] = SDE_PORTD_HOTPLUG
	82	+ [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
66	83	};
67	84
68	85	static const u32 hpd_cpt[HPD_NUM_PINS] = {
..	..	@@ -70,7 +87,7 @@
70	87	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71	88	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72	89	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73		- [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
	90	+ [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
74	91	};
75	92
76	93	static const u32 hpd_spt[HPD_NUM_PINS] = {
..	..	@@ -78,7 +95,7 @@
78	95	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79	96	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80	97	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81		- [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
	98	+ [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
82	99	};
83	100
84	101	static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
..	..	@@ -87,7 +104,7 @@
87	104	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88	105	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89	106	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90		- [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
	107	+ [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
91	108	};
92	109
93	110	static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
..	..	@@ -96,7 +113,7 @@
96	113	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97	114	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98	115	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99		- [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
	116	+ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
100	117	};
101	118
102	119	static const u32 hpd_status_i915[HPD_NUM_PINS] = {
..	..	@@ -105,132 +122,180 @@
105	122	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106	123	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107	124	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108		- [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
	125	+ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
109	126	};
110	127
111		-/* BXT hpd list */
112	128	static const u32 hpd_bxt[HPD_NUM_PINS] = {
113	129	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114	130	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115		- [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
	131	+ [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
116	132	};
117	133
118	134	static const u32 hpd_gen11[HPD_NUM_PINS] = {
119		- [HPD_PORT_C] = GEN11_TC1_HOTPLUG \| GEN11_TBT1_HOTPLUG,
120		- [HPD_PORT_D] = GEN11_TC2_HOTPLUG \| GEN11_TBT2_HOTPLUG,
121		- [HPD_PORT_E] = GEN11_TC3_HOTPLUG \| GEN11_TBT3_HOTPLUG,
122		- [HPD_PORT_F] = GEN11_TC4_HOTPLUG \| GEN11_TBT4_HOTPLUG
	135	+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) \| GEN11_TBT_HOTPLUG(PORT_TC1),
	136	+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) \| GEN11_TBT_HOTPLUG(PORT_TC2),
	137	+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) \| GEN11_TBT_HOTPLUG(PORT_TC3),
	138	+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) \| GEN11_TBT_HOTPLUG(PORT_TC4),
	139	+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) \| GEN11_TBT_HOTPLUG(PORT_TC5),
	140	+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) \| GEN11_TBT_HOTPLUG(PORT_TC6),
123	141	};
124	142
125	143	static const u32 hpd_icp[HPD_NUM_PINS] = {
126		- [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
127		- [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
128		- [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
129		- [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
130		- [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
131		- [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
	144	+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
	145	+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
	146	+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
	147	+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
	148	+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
	149	+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
	150	+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
	151	+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
	152	+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
132	153	};
133	154
134		-/* IIR can theoretically queue up two events. Be paranoid. */
135		-#define GEN8_IRQ_RESET_NDX(type, which) do { \
136		- I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
137		- POSTING_READ(GEN8_##type##_IMR(which)); \
138		- I915_WRITE(GEN8_##type##_IER(which), 0); \
139		- I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
140		- POSTING_READ(GEN8_##type##_IIR(which)); \
141		- I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
142		- POSTING_READ(GEN8_##type##_IIR(which)); \
143		-} while (0)
	155	+static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
	156	+{
	157	+ struct i915_hotplug *hpd = &dev_priv->hotplug;
144	158
145		-#define GEN3_IRQ_RESET(type) do { \
146		- I915_WRITE(type##IMR, 0xffffffff); \
147		- POSTING_READ(type##IMR); \
148		- I915_WRITE(type##IER, 0); \
149		- I915_WRITE(type##IIR, 0xffffffff); \
150		- POSTING_READ(type##IIR); \
151		- I915_WRITE(type##IIR, 0xffffffff); \
152		- POSTING_READ(type##IIR); \
153		-} while (0)
	159	+ if (HAS_GMCH(dev_priv)) {
	160	+ if (IS_G4X(dev_priv) \|\| IS_VALLEYVIEW(dev_priv) \|\|
	161	+ IS_CHERRYVIEW(dev_priv))
	162	+ hpd->hpd = hpd_status_g4x;
	163	+ else
	164	+ hpd->hpd = hpd_status_i915;
	165	+ return;
	166	+ }
154	167
155		-#define GEN2_IRQ_RESET(type) do { \
156		- I915_WRITE16(type##IMR, 0xffff); \
157		- POSTING_READ16(type##IMR); \
158		- I915_WRITE16(type##IER, 0); \
159		- I915_WRITE16(type##IIR, 0xffff); \
160		- POSTING_READ16(type##IIR); \
161		- I915_WRITE16(type##IIR, 0xffff); \
162		- POSTING_READ16(type##IIR); \
163		-} while (0)
	168	+ if (INTEL_GEN(dev_priv) >= 11)
	169	+ hpd->hpd = hpd_gen11;
	170	+ else if (IS_GEN9_LP(dev_priv))
	171	+ hpd->hpd = hpd_bxt;
	172	+ else if (INTEL_GEN(dev_priv) >= 8)
	173	+ hpd->hpd = hpd_bdw;
	174	+ else if (INTEL_GEN(dev_priv) >= 7)
	175	+ hpd->hpd = hpd_ivb;
	176	+ else
	177	+ hpd->hpd = hpd_ilk;
	178	+
	179	+ if (!HAS_PCH_SPLIT(dev_priv) \|\| HAS_PCH_NOP(dev_priv))
	180	+ return;
	181	+
	182	+ if (HAS_PCH_TGP(dev_priv) \|\| HAS_PCH_JSP(dev_priv) \|\|
	183	+ HAS_PCH_ICP(dev_priv) \|\| HAS_PCH_MCC(dev_priv))
	184	+ hpd->pch_hpd = hpd_icp;
	185	+ else if (HAS_PCH_CNP(dev_priv) \|\| HAS_PCH_SPT(dev_priv))
	186	+ hpd->pch_hpd = hpd_spt;
	187	+ else if (HAS_PCH_LPT(dev_priv) \|\| HAS_PCH_CPT(dev_priv))
	188	+ hpd->pch_hpd = hpd_cpt;
	189	+ else if (HAS_PCH_IBX(dev_priv))
	190	+ hpd->pch_hpd = hpd_ibx;
	191	+ else
	192	+ MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
	193	+}
	194	+
	195	+static void
	196	+intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
	197	+{
	198	+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
	199	+
	200	+ drm_crtc_handle_vblank(&crtc->base);
	201	+}
	202	+
	203	+void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
	204	+ i915_reg_t iir, i915_reg_t ier)
	205	+{
	206	+ intel_uncore_write(uncore, imr, 0xffffffff);
	207	+ intel_uncore_posting_read(uncore, imr);
	208	+
	209	+ intel_uncore_write(uncore, ier, 0);
	210	+
	211	+ /* IIR can theoretically queue up two events. Be paranoid. */
	212	+ intel_uncore_write(uncore, iir, 0xffffffff);
	213	+ intel_uncore_posting_read(uncore, iir);
	214	+ intel_uncore_write(uncore, iir, 0xffffffff);
	215	+ intel_uncore_posting_read(uncore, iir);
	216	+}
	217	+
	218	+void gen2_irq_reset(struct intel_uncore *uncore)
	219	+{
	220	+ intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
	221	+ intel_uncore_posting_read16(uncore, GEN2_IMR);
	222	+
	223	+ intel_uncore_write16(uncore, GEN2_IER, 0);
	224	+
	225	+ /* IIR can theoretically queue up two events. Be paranoid. */
	226	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	227	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
	228	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	229	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
	230	+}
164	231
165	232	/*
166	233	* We should clear IMR at preinstall/uninstall, and just check at postinstall.
167	234	*/
168		-static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
169		- i915_reg_t reg)
	235	+static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
170	236	{
171		- u32 val = I915_READ(reg);
	237	+ u32 val = intel_uncore_read(uncore, reg);
172	238
173	239	if (val == 0)
174	240	return;
175	241
176		- WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
177		- i915_mmio_reg_offset(reg), val);
178		- I915_WRITE(reg, 0xffffffff);
179		- POSTING_READ(reg);
180		- I915_WRITE(reg, 0xffffffff);
181		- POSTING_READ(reg);
	242	+ drm_WARN(&uncore->i915->drm, 1,
	243	+ "Interrupt register 0x%x is not zero: 0x%08x\n",
	244	+ i915_mmio_reg_offset(reg), val);
	245	+ intel_uncore_write(uncore, reg, 0xffffffff);
	246	+ intel_uncore_posting_read(uncore, reg);
	247	+ intel_uncore_write(uncore, reg, 0xffffffff);
	248	+ intel_uncore_posting_read(uncore, reg);
182	249	}
183	250
184		-static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
185		- i915_reg_t reg)
	251	+static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
186	252	{
187		- u16 val = I915_READ16(reg);
	253	+ u16 val = intel_uncore_read16(uncore, GEN2_IIR);
188	254
189	255	if (val == 0)
190	256	return;
191	257
192		- WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
193		- i915_mmio_reg_offset(reg), val);
194		- I915_WRITE16(reg, 0xffff);
195		- POSTING_READ16(reg);
196		- I915_WRITE16(reg, 0xffff);
197		- POSTING_READ16(reg);
	258	+ drm_WARN(&uncore->i915->drm, 1,
	259	+ "Interrupt register 0x%x is not zero: 0x%08x\n",
	260	+ i915_mmio_reg_offset(GEN2_IIR), val);
	261	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	262	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
	263	+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
	264	+ intel_uncore_posting_read16(uncore, GEN2_IIR);
198	265	}
199	266
200		-#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
201		- gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
202		- I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
203		- I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
204		- POSTING_READ(GEN8_##type##_IMR(which)); \
205		-} while (0)
	267	+void gen3_irq_init(struct intel_uncore *uncore,
	268	+ i915_reg_t imr, u32 imr_val,
	269	+ i915_reg_t ier, u32 ier_val,
	270	+ i915_reg_t iir)
	271	+{
	272	+ gen3_assert_iir_is_zero(uncore, iir);
206	273
207		-#define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
208		- gen3_assert_iir_is_zero(dev_priv, type##IIR); \
209		- I915_WRITE(type##IER, (ier_val)); \
210		- I915_WRITE(type##IMR, (imr_val)); \
211		- POSTING_READ(type##IMR); \
212		-} while (0)
	274	+ intel_uncore_write(uncore, ier, ier_val);
	275	+ intel_uncore_write(uncore, imr, imr_val);
	276	+ intel_uncore_posting_read(uncore, imr);
	277	+}
213	278
214		-#define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
215		- gen2_assert_iir_is_zero(dev_priv, type##IIR); \
216		- I915_WRITE16(type##IER, (ier_val)); \
217		- I915_WRITE16(type##IMR, (imr_val)); \
218		- POSTING_READ16(type##IMR); \
219		-} while (0)
	279	+void gen2_irq_init(struct intel_uncore *uncore,
	280	+ u32 imr_val, u32 ier_val)
	281	+{
	282	+ gen2_assert_iir_is_zero(uncore);
220	283
221		-static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
222		-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
	284	+ intel_uncore_write16(uncore, GEN2_IER, ier_val);
	285	+ intel_uncore_write16(uncore, GEN2_IMR, imr_val);
	286	+ intel_uncore_posting_read16(uncore, GEN2_IMR);
	287	+}
223	288
224	289	/* For display hotplug interrupt */
225	290	static inline void
226	291	i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
227		- uint32_t mask,
228		- uint32_t bits)
	292	+ u32 mask,
	293	+ u32 bits)
229	294	{
230		- uint32_t val;
	295	+ u32 val;
231	296
232	297	lockdep_assert_held(&dev_priv->irq_lock);
233		- WARN_ON(bits & ~mask);
	298	+ drm_WARN_ON(&dev_priv->drm, bits & ~mask);
234	299
235	300	val = I915_READ(PORT_HOTPLUG_EN);
236	301	val &= ~mask;
..	..	@@ -251,47 +316,12 @@
251	316	* version is also available.
252	317	*/
253	318	void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
254		- uint32_t mask,
255		- uint32_t bits)
	319	+ u32 mask,
	320	+ u32 bits)
256	321	{
257	322	spin_lock_irq(&dev_priv->irq_lock);
258	323	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
259	324	spin_unlock_irq(&dev_priv->irq_lock);
260		-}
261		-
262		-static u32
263		-gen11_gt_engine_identity(struct drm_i915_private * const i915,
264		- const unsigned int bank, const unsigned int bit);
265		-
266		-static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
267		- const unsigned int bank,
268		- const unsigned int bit)
269		-{
270		- void __iomem * const regs = i915->regs;
271		- u32 dw;
272		-
273		- lockdep_assert_held(&i915->irq_lock);
274		-
275		- dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
276		- if (dw & BIT(bit)) {
277		- /*
278		- * According to the BSpec, DW_IIR bits cannot be cleared without
279		- * first servicing the Selector & Shared IIR registers.
280		- */
281		- gen11_gt_engine_identity(i915, bank, bit);
282		-
283		- /*
284		- * We locked GT INT DW by reading it. If we want to (try
285		- * to) recover from this succesfully, we need to clear
286		- * our bit, otherwise we are locking the register for
287		- * everybody.
288		- */
289		- raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
290		-
291		- return true;
292		- }
293		-
294		- return false;
295	325	}
296	326
297	327	/**
..	..	@@ -301,16 +331,16 @@
301	331	* @enabled_irq_mask: mask of interrupt bits to enable
302	332	*/
303	333	void ilk_update_display_irq(struct drm_i915_private *dev_priv,
304		- uint32_t interrupt_mask,
305		- uint32_t enabled_irq_mask)
	334	+ u32 interrupt_mask,
	335	+ u32 enabled_irq_mask)
306	336	{
307		- uint32_t new_val;
	337	+ u32 new_val;
308	338
309	339	lockdep_assert_held(&dev_priv->irq_lock);
310	340
311		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	341	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
312	342
313		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	343	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
314	344	return;
315	345
316	346	new_val = dev_priv->irq_mask;
..	..	@@ -325,270 +355,23 @@
325	355	}
326	356
327	357	/**
328		- * ilk_update_gt_irq - update GTIMR
329		- * @dev_priv: driver private
330		- * @interrupt_mask: mask of interrupt bits to update
331		- * @enabled_irq_mask: mask of interrupt bits to enable
332		- */
333		-static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
334		- uint32_t interrupt_mask,
335		- uint32_t enabled_irq_mask)
336		-{
337		- lockdep_assert_held(&dev_priv->irq_lock);
338		-
339		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
340		-
341		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
342		- return;
343		-
344		- dev_priv->gt_irq_mask &= ~interrupt_mask;
345		- dev_priv->gt_irq_mask \|= (~enabled_irq_mask & interrupt_mask);
346		- I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
347		-}
348		-
349		-void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
350		-{
351		- ilk_update_gt_irq(dev_priv, mask, mask);
352		- POSTING_READ_FW(GTIMR);
353		-}
354		-
355		-void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
356		-{
357		- ilk_update_gt_irq(dev_priv, mask, 0);
358		-}
359		-
360		-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
361		-{
362		- WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
363		-
364		- return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
365		-}
366		-
367		-static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
368		-{
369		- if (INTEL_GEN(dev_priv) >= 11)
370		- return GEN11_GPM_WGBOXPERF_INTR_MASK;
371		- else if (INTEL_GEN(dev_priv) >= 8)
372		- return GEN8_GT_IMR(2);
373		- else
374		- return GEN6_PMIMR;
375		-}
376		-
377		-static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
378		-{
379		- if (INTEL_GEN(dev_priv) >= 11)
380		- return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
381		- else if (INTEL_GEN(dev_priv) >= 8)
382		- return GEN8_GT_IER(2);
383		- else
384		- return GEN6_PMIER;
385		-}
386		-
387		-/**
388		- * snb_update_pm_irq - update GEN6_PMIMR
389		- * @dev_priv: driver private
390		- * @interrupt_mask: mask of interrupt bits to update
391		- * @enabled_irq_mask: mask of interrupt bits to enable
392		- */
393		-static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
394		- uint32_t interrupt_mask,
395		- uint32_t enabled_irq_mask)
396		-{
397		- uint32_t new_val;
398		-
399		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
400		-
401		- lockdep_assert_held(&dev_priv->irq_lock);
402		-
403		- new_val = dev_priv->pm_imr;
404		- new_val &= ~interrupt_mask;
405		- new_val \|= (~enabled_irq_mask & interrupt_mask);
406		-
407		- if (new_val != dev_priv->pm_imr) {
408		- dev_priv->pm_imr = new_val;
409		- I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
410		- POSTING_READ(gen6_pm_imr(dev_priv));
411		- }
412		-}
413		-
414		-void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
415		-{
416		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
417		- return;
418		-
419		- snb_update_pm_irq(dev_priv, mask, mask);
420		-}
421		-
422		-static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
423		-{
424		- snb_update_pm_irq(dev_priv, mask, 0);
425		-}
426		-
427		-void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
428		-{
429		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
430		- return;
431		-
432		- __gen6_mask_pm_irq(dev_priv, mask);
433		-}
434		-
435		-static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
436		-{
437		- i915_reg_t reg = gen6_pm_iir(dev_priv);
438		-
439		- lockdep_assert_held(&dev_priv->irq_lock);
440		-
441		- I915_WRITE(reg, reset_mask);
442		- I915_WRITE(reg, reset_mask);
443		- POSTING_READ(reg);
444		-}
445		-
446		-static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
447		-{
448		- lockdep_assert_held(&dev_priv->irq_lock);
449		-
450		- dev_priv->pm_ier \|= enable_mask;
451		- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
452		- gen6_unmask_pm_irq(dev_priv, enable_mask);
453		- /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
454		-}
455		-
456		-static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
457		-{
458		- lockdep_assert_held(&dev_priv->irq_lock);
459		-
460		- dev_priv->pm_ier &= ~disable_mask;
461		- __gen6_mask_pm_irq(dev_priv, disable_mask);
462		- I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
463		- /* though a barrier is missing here, but don't really need a one */
464		-}
465		-
466		-void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
467		-{
468		- spin_lock_irq(&dev_priv->irq_lock);
469		-
470		- while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
471		- ;
472		-
473		- dev_priv->gt_pm.rps.pm_iir = 0;
474		-
475		- spin_unlock_irq(&dev_priv->irq_lock);
476		-}
477		-
478		-void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
479		-{
480		- spin_lock_irq(&dev_priv->irq_lock);
481		- gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
482		- dev_priv->gt_pm.rps.pm_iir = 0;
483		- spin_unlock_irq(&dev_priv->irq_lock);
484		-}
485		-
486		-void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
487		-{
488		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
489		-
490		- if (READ_ONCE(rps->interrupts_enabled))
491		- return;
492		-
493		- spin_lock_irq(&dev_priv->irq_lock);
494		- WARN_ON_ONCE(rps->pm_iir);
495		-
496		- if (INTEL_GEN(dev_priv) >= 11)
497		- WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
498		- else
499		- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
500		-
501		- rps->interrupts_enabled = true;
502		- gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
503		-
504		- spin_unlock_irq(&dev_priv->irq_lock);
505		-}
506		-
507		-void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
508		-{
509		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
510		-
511		- if (!READ_ONCE(rps->interrupts_enabled))
512		- return;
513		-
514		- spin_lock_irq(&dev_priv->irq_lock);
515		- rps->interrupts_enabled = false;
516		-
517		- I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
518		-
519		- gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
520		-
521		- spin_unlock_irq(&dev_priv->irq_lock);
522		- synchronize_irq(dev_priv->drm.irq);
523		-
524		- /* Now that we will not be generating any more work, flush any
525		- * outstanding tasks. As we are called on the RPS idle path,
526		- * we will reset the GPU to minimum frequencies, so the current
527		- * state of the worker can be discarded.
528		- */
529		- cancel_work_sync(&rps->work);
530		- if (INTEL_GEN(dev_priv) >= 11)
531		- gen11_reset_rps_interrupts(dev_priv);
532		- else
533		- gen6_reset_rps_interrupts(dev_priv);
534		-}
535		-
536		-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
537		-{
538		- assert_rpm_wakelock_held(dev_priv);
539		-
540		- spin_lock_irq(&dev_priv->irq_lock);
541		- gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
542		- spin_unlock_irq(&dev_priv->irq_lock);
543		-}
544		-
545		-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
546		-{
547		- assert_rpm_wakelock_held(dev_priv);
548		-
549		- spin_lock_irq(&dev_priv->irq_lock);
550		- if (!dev_priv->guc.interrupts_enabled) {
551		- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
552		- dev_priv->pm_guc_events);
553		- dev_priv->guc.interrupts_enabled = true;
554		- gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
555		- }
556		- spin_unlock_irq(&dev_priv->irq_lock);
557		-}
558		-
559		-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
560		-{
561		- assert_rpm_wakelock_held(dev_priv);
562		-
563		- spin_lock_irq(&dev_priv->irq_lock);
564		- dev_priv->guc.interrupts_enabled = false;
565		-
566		- gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
567		-
568		- spin_unlock_irq(&dev_priv->irq_lock);
569		- synchronize_irq(dev_priv->drm.irq);
570		-
571		- gen9_reset_guc_interrupts(dev_priv);
572		-}
573		-
574		-/**
575	358	* bdw_update_port_irq - update DE port interrupt
576	359	* @dev_priv: driver private
577	360	* @interrupt_mask: mask of interrupt bits to update
578	361	* @enabled_irq_mask: mask of interrupt bits to enable
579	362	*/
580	363	static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
581		- uint32_t interrupt_mask,
582		- uint32_t enabled_irq_mask)
	364	+ u32 interrupt_mask,
	365	+ u32 enabled_irq_mask)
583	366	{
584		- uint32_t new_val;
585		- uint32_t old_val;
	367	+ u32 new_val;
	368	+ u32 old_val;
586	369
587	370	lockdep_assert_held(&dev_priv->irq_lock);
588	371
589		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	372	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
590	373
591		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	374	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
592	375	return;
593	376
594	377	old_val = I915_READ(GEN8_DE_PORT_IMR);
..	..	@@ -612,16 +395,16 @@
612	395	*/
613	396	void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
614	397	enum pipe pipe,
615		- uint32_t interrupt_mask,
616		- uint32_t enabled_irq_mask)
	398	+ u32 interrupt_mask,
	399	+ u32 enabled_irq_mask)
617	400	{
618		- uint32_t new_val;
	401	+ u32 new_val;
619	402
620	403	lockdep_assert_held(&dev_priv->irq_lock);
621	404
622		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	405	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
623	406
624		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	407	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
625	408	return;
626	409
627	410	new_val = dev_priv->de_irq_mask[pipe];
..	..	@@ -642,18 +425,18 @@
642	425	* @enabled_irq_mask: mask of interrupt bits to enable
643	426	*/
644	427	void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
645		- uint32_t interrupt_mask,
646		- uint32_t enabled_irq_mask)
	428	+ u32 interrupt_mask,
	429	+ u32 enabled_irq_mask)
647	430	{
648		- uint32_t sdeimr = I915_READ(SDEIMR);
	431	+ u32 sdeimr = I915_READ(SDEIMR);
649	432	sdeimr &= ~interrupt_mask;
650	433	sdeimr \|= (~enabled_irq_mask & interrupt_mask);
651	434
652		- WARN_ON(enabled_irq_mask & ~interrupt_mask);
	435	+ drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
653	436
654	437	lockdep_assert_held(&dev_priv->irq_lock);
655	438
656		- if (WARN_ON(!intel_irqs_enabled(dev_priv)))
	439	+ if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
657	440	return;
658	441
659	442	I915_WRITE(SDEIMR, sdeimr);
..	..	@@ -675,13 +458,15 @@
675	458	* On pipe A we don't support the PSR interrupt yet,
676	459	* on pipe B and C the same bit MBZ.
677	460	*/
678		- if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
	461	+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
	462	+ status_mask & PIPE_A_PSR_STATUS_VLV))
679	463	return 0;
680	464	/*
681	465	* On pipe B and C we don't support the PSR interrupt yet, on pipe
682	466	* A the same bit is for perf counters which we don't use either.
683	467	*/
684		- if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
	468	+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
	469	+ status_mask & PIPE_B_PSR_STATUS_VLV))
685	470	return 0;
686	471
687	472	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS \|
..	..	@@ -693,10 +478,11 @@
693	478	enable_mask \|= SPRITE1_FLIP_DONE_INT_EN_VLV;
694	479
695	480	out:
696		- WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK \|\|
697		- status_mask & ~PIPESTAT_INT_STATUS_MASK,
698		- "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
699		- pipe_name(pipe), enable_mask, status_mask);
	481	+ drm_WARN_ONCE(&dev_priv->drm,
	482	+ enable_mask & ~PIPESTAT_INT_ENABLE_MASK \|\|
	483	+ status_mask & ~PIPESTAT_INT_STATUS_MASK,
	484	+ "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
	485	+ pipe_name(pipe), enable_mask, status_mask);
700	486
701	487	return enable_mask;
702	488	}
..	..	@@ -707,12 +493,12 @@
707	493	i915_reg_t reg = PIPESTAT(pipe);
708	494	u32 enable_mask;
709	495
710		- WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
711		- "pipe %c: status_mask=0x%x\n",
712		- pipe_name(pipe), status_mask);
	496	+ drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
	497	+ "pipe %c: status_mask=0x%x\n",
	498	+ pipe_name(pipe), status_mask);
713	499
714	500	lockdep_assert_held(&dev_priv->irq_lock);
715		- WARN_ON(!intel_irqs_enabled(dev_priv));
	501	+ drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
716	502
717	503	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
718	504	return;
..	..	@@ -730,12 +516,12 @@
730	516	i915_reg_t reg = PIPESTAT(pipe);
731	517	u32 enable_mask;
732	518
733		- WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
734		- "pipe %c: status_mask=0x%x\n",
735		- pipe_name(pipe), status_mask);
	519	+ drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
	520	+ "pipe %c: status_mask=0x%x\n",
	521	+ pipe_name(pipe), status_mask);
736	522
737	523	lockdep_assert_held(&dev_priv->irq_lock);
738		- WARN_ON(!intel_irqs_enabled(dev_priv));
	524	+ drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
739	525
740	526	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
741	527	return;
..	..	@@ -747,13 +533,21 @@
747	533	POSTING_READ(reg);
748	534	}
749	535
	536	+static bool i915_has_asle(struct drm_i915_private *dev_priv)
	537	+{
	538	+ if (!dev_priv->opregion.asle)
	539	+ return false;
	540	+
	541	+ return IS_PINEVIEW(dev_priv) \|\| IS_MOBILE(dev_priv);
	542	+}
	543	+
750	544	/**
751	545	* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
752	546	* @dev_priv: i915 device private
753	547	*/
754	548	static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
755	549	{
756		- if (!dev_priv->opregion.asle \|\| !IS_MOBILE(dev_priv))
	550	+ if (!i915_has_asle(dev_priv))
757	551	return;
758	552
759	553	spin_lock_irq(&dev_priv->irq_lock);
..	..	@@ -819,13 +613,29 @@
819	613	/* Called from drm generic code, passed a 'crtc', which
820	614	* we use as a pipe index
821	615	*/
822		-static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
	616	+u32 i915_get_vblank_counter(struct drm_crtc *crtc)
823	617	{
824		- struct drm_i915_private *dev_priv = to_i915(dev);
	618	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	619	+ struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
	620	+ const struct drm_display_mode *mode = &vblank->hwmode;
	621	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
825	622	i915_reg_t high_frame, low_frame;
826	623	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
827		- const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;
828	624	unsigned long irqflags;
	625	+
	626	+ /*
	627	+ * On i965gm TV output the frame counter only works up to
	628	+ * the point when we enable the TV encoder. After that the
	629	+ * frame counter ceases to work and reads zero. We need a
	630	+ * vblank wait before enabling the TV encoder and so we
	631	+ * have to enable vblank interrupts while the frame counter
	632	+ * is still in a working state. However the core vblank code
	633	+ * does not like us returning non-zero frame counter values
	634	+ * when we've told it that we don't have a working frame
	635	+ * counter. Thus we must stop non-zero values leaking out.
	636	+ */
	637	+ if (!vblank->max_vblank_count)
	638	+ return 0;
829	639
830	640	htotal = mode->crtc_htotal;
831	641	hsync_start = mode->crtc_hsync_start;
..	..	@@ -850,9 +660,9 @@
850	660	* register.
851	661	*/
852	662	do {
853		- high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
854		- low = I915_READ_FW(low_frame);
855		- high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
	663	+ high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
	664	+ low = intel_de_read_fw(dev_priv, low_frame);
	665	+ high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
856	666	} while (high1 != high2);
857	667
858	668	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
..	..	@@ -869,9 +679,10 @@
869	679	return (((high1 << 8) \| low) + (pixel >= vbl_start)) & 0xffffff;
870	680	}
871	681
872		-static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
	682	+u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
873	683	{
874		- struct drm_i915_private *dev_priv = to_i915(dev);
	684	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	685	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
875	686
876	687	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
877	688	}
..	..	@@ -908,15 +719,17 @@
908	719	* pipe frame time stamp. The time stamp value
909	720	* is sampled at every start of vertical blank.
910	721	*/
911		- scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
	722	+ scan_prev_time = intel_de_read_fw(dev_priv,
	723	+ PIPE_FRMTMSTMP(crtc->pipe));
912	724
913	725	/*
914	726	* The TIMESTAMP_CTR register has the current
915	727	* time stamp value.
916	728	*/
917		- scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
	729	+ scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
918	730
919		- scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
	731	+ scan_post_time = intel_de_read_fw(dev_priv,
	732	+ PIPE_FRMTMSTMP(crtc->pipe));
920	733	} while (scan_post_time != scan_prev_time);
921	734
922	735	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
..	..	@@ -927,7 +740,10 @@
927	740	return scanline;
928	741	}
929	742
930		-/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
	743	+/*
	744	+ * intel_de_read_fw(), only for fast reads of display block, no need for
	745	+ * forcewake etc.
	746	+ */
931	747	static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
932	748	{
933	749	struct drm_device *dev = crtc->base.dev;
..	..	@@ -943,17 +759,17 @@
943	759	vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
944	760	mode = &vblank->hwmode;
945	761
946		- if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
	762	+ if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
947	763	return __intel_get_crtc_scanline_from_timestamp(crtc);
948	764
949	765	vtotal = mode->crtc_vtotal;
950	766	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
951	767	vtotal /= 2;
952	768
953		- if (IS_GEN2(dev_priv))
954		- position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
	769	+ if (IS_GEN(dev_priv, 2))
	770	+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
955	771	else
956		- position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
	772	+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
957	773
958	774	/*
959	775	* On HSW, the DSL reg (0x70000) appears to return 0 if we
..	..	@@ -972,7 +788,7 @@
972	788
973	789	for (i = 0; i < 100; i++) {
974	790	udelay(1);
975		- temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
	791	+ temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
976	792	if (temp != position) {
977	793	position = temp;
978	794	break;
..	..	@@ -987,21 +803,27 @@
987	803	return (position + crtc->scanline_offset) % vtotal;
988	804	}
989	805
990		-static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
991		- bool in_vblank_irq, int vpos, int hpos,
	806	+static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
	807	+ bool in_vblank_irq,
	808	+ int vpos, int hpos,
992	809	ktime_t stime, ktime_t etime,
993	810	const struct drm_display_mode *mode)
994	811	{
	812	+ struct drm_device *dev = _crtc->dev;
995	813	struct drm_i915_private *dev_priv = to_i915(dev);
996		- struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
997		- pipe);
	814	+ struct intel_crtc *crtc = to_intel_crtc(_crtc);
	815	+ enum pipe pipe = crtc->pipe;
998	816	int position;
999	817	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
1000	818	unsigned long irqflags;
	819	+ bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 \|\|
	820	+ IS_G4X(dev_priv) \|\| IS_GEN(dev_priv, 2) \|\|
	821	+ crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1001	822
1002		- if (WARN_ON(!mode->crtc_clock)) {
1003		- DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
1004		- "pipe %c\n", pipe_name(pipe));
	823	+ if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
	824	+ drm_dbg(&dev_priv->drm,
	825	+ "trying to get scanoutpos for disabled "
	826	+ "pipe %c\n", pipe_name(pipe));
1005	827	return false;
1006	828	}
1007	829
..	..	@@ -1025,23 +847,22 @@
1025	847	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1026	848
1027	849	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1028		- preempt_disable_rt();
1029	850
1030	851	/* Get optional system timestamp before query. */
1031	852	if (stime)
1032	853	*stime = ktime_get();
1033	854
1034		- if (IS_GEN2(dev_priv) \|\| IS_G4X(dev_priv) \|\| INTEL_GEN(dev_priv) >= 5) {
	855	+ if (use_scanline_counter) {
1035	856	/* No obvious pixelcount register. Only query vertical
1036	857	* scanout position from Display scan line register.
1037	858	*/
1038		- position = __intel_get_crtc_scanline(intel_crtc);
	859	+ position = __intel_get_crtc_scanline(crtc);
1039	860	} else {
1040	861	/* Have access to pixelcount since start of frame.
1041	862	* We can split this into vertical and horizontal
1042	863	* scanout position.
1043	864	*/
1044		- position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
	865	+ position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1045	866
1046	867	/* convert to pixel counts */
1047	868	vbl_start *= htotal;
..	..	@@ -1077,7 +898,6 @@
1077	898	*etime = ktime_get();
1078	899
1079	900	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1080		- preempt_enable_rt();
1081	901
1082	902	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1083	903
..	..	@@ -1092,7 +912,7 @@
1092	912	else
1093	913	position += vtotal - vbl_end;
1094	914
1095		- if (IS_GEN2(dev_priv) \|\| IS_G4X(dev_priv) \|\| INTEL_GEN(dev_priv) >= 5) {
	915	+ if (use_scanline_counter) {
1096	916	*vpos = position;
1097	917	*hpos = 0;
1098	918	} else {
..	..	@@ -1101,6 +921,14 @@
1101	921	}
1102	922
1103	923	return true;
	924	+}
	925	+
	926	+bool intel_crtc_get_vblank_timestamp(struct drm_crtc crtc, int max_error,
	927	+ ktime_t *vblank_time, bool in_vblank_irq)
	928	+{
	929	+ return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
	930	+ crtc, max_error, vblank_time, in_vblank_irq,
	931	+ i915_get_crtc_scanoutpos);
1104	932	}
1105	933
1106	934	int intel_get_crtc_scanline(struct intel_crtc *crtc)
..	..	@@ -1116,255 +944,8 @@
1116	944	return position;
1117	945	}
1118	946
1119		-static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1120		-{
1121		- u32 busy_up, busy_down, max_avg, min_avg;
1122		- u8 new_delay;
1123		-
1124		- spin_lock(&mchdev_lock);
1125		-
1126		- I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1127		-
1128		- new_delay = dev_priv->ips.cur_delay;
1129		-
1130		- I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1131		- busy_up = I915_READ(RCPREVBSYTUPAVG);
1132		- busy_down = I915_READ(RCPREVBSYTDNAVG);
1133		- max_avg = I915_READ(RCBMAXAVG);
1134		- min_avg = I915_READ(RCBMINAVG);
1135		-
1136		- /* Handle RCS change request from hw */
1137		- if (busy_up > max_avg) {
1138		- if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1139		- new_delay = dev_priv->ips.cur_delay - 1;
1140		- if (new_delay < dev_priv->ips.max_delay)
1141		- new_delay = dev_priv->ips.max_delay;
1142		- } else if (busy_down < min_avg) {
1143		- if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1144		- new_delay = dev_priv->ips.cur_delay + 1;
1145		- if (new_delay > dev_priv->ips.min_delay)
1146		- new_delay = dev_priv->ips.min_delay;
1147		- }
1148		-
1149		- if (ironlake_set_drps(dev_priv, new_delay))
1150		- dev_priv->ips.cur_delay = new_delay;
1151		-
1152		- spin_unlock(&mchdev_lock);
1153		-
1154		- return;
1155		-}
1156		-
1157		-static void notify_ring(struct intel_engine_cs *engine)
1158		-{
1159		- const u32 seqno = intel_engine_get_seqno(engine);
1160		- struct i915_request *rq = NULL;
1161		- struct task_struct *tsk = NULL;
1162		- struct intel_wait *wait;
1163		-
1164		- if (unlikely(!engine->breadcrumbs.irq_armed))
1165		- return;
1166		-
1167		- rcu_read_lock();
1168		-
1169		- spin_lock(&engine->breadcrumbs.irq_lock);
1170		- wait = engine->breadcrumbs.irq_wait;
1171		- if (wait) {
1172		- /*
1173		- * We use a callback from the dma-fence to submit
1174		- * requests after waiting on our own requests. To
1175		- * ensure minimum delay in queuing the next request to
1176		- * hardware, signal the fence now rather than wait for
1177		- * the signaler to be woken up. We still wake up the
1178		- * waiter in order to handle the irq-seqno coherency
1179		- * issues (we may receive the interrupt before the
1180		- * seqno is written, see __i915_request_irq_complete())
1181		- * and to handle coalescing of multiple seqno updates
1182		- * and many waiters.
1183		- */
1184		- if (i915_seqno_passed(seqno, wait->seqno)) {
1185		- struct i915_request *waiter = wait->request;
1186		-
1187		- if (waiter &&
1188		- !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1189		- &waiter->fence.flags) &&
1190		- intel_wait_check_request(wait, waiter))
1191		- rq = i915_request_get(waiter);
1192		-
1193		- tsk = wait->tsk;
1194		- } else {
1195		- if (engine->irq_seqno_barrier &&
1196		- i915_seqno_passed(seqno, wait->seqno - 1)) {
1197		- set_bit(ENGINE_IRQ_BREADCRUMB,
1198		- &engine->irq_posted);
1199		- tsk = wait->tsk;
1200		- }
1201		- }
1202		-
1203		- engine->breadcrumbs.irq_count++;
1204		- } else {
1205		- if (engine->breadcrumbs.irq_armed)
1206		- __intel_engine_disarm_breadcrumbs(engine);
1207		- }
1208		- spin_unlock(&engine->breadcrumbs.irq_lock);
1209		-
1210		- if (rq) {
1211		- spin_lock(&rq->lock);
1212		- dma_fence_signal_locked(&rq->fence);
1213		- GEM_BUG_ON(!i915_request_completed(rq));
1214		- spin_unlock(&rq->lock);
1215		-
1216		- i915_request_put(rq);
1217		- }
1218		-
1219		- if (tsk && tsk->state & TASK_NORMAL)
1220		- wake_up_process(tsk);
1221		-
1222		- rcu_read_unlock();
1223		-
1224		- trace_intel_engine_notify(engine, wait);
1225		-}
1226		-
1227		-static void vlv_c0_read(struct drm_i915_private *dev_priv,
1228		- struct intel_rps_ei *ei)
1229		-{
1230		- ei->ktime = ktime_get_raw();
1231		- ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1232		- ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1233		-}
1234		-
1235		-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1236		-{
1237		- memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1238		-}
1239		-
1240		-static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1241		-{
1242		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
1243		- const struct intel_rps_ei *prev = &rps->ei;
1244		- struct intel_rps_ei now;
1245		- u32 events = 0;
1246		-
1247		- if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1248		- return 0;
1249		-
1250		- vlv_c0_read(dev_priv, &now);
1251		-
1252		- if (prev->ktime) {
1253		- u64 time, c0;
1254		- u32 render, media;
1255		-
1256		- time = ktime_us_delta(now.ktime, prev->ktime);
1257		-
1258		- time *= dev_priv->czclk_freq;
1259		-
1260		- /* Workload can be split between render + media,
1261		- * e.g. SwapBuffers being blitted in X after being rendered in
1262		- * mesa. To account for this we need to combine both engines
1263		- * into our activity counter.
1264		- */
1265		- render = now.render_c0 - prev->render_c0;
1266		- media = now.media_c0 - prev->media_c0;
1267		- c0 = max(render, media);
1268		- c0 = 1000 100 << 8; /* to usecs and scale to threshold% */
1269		-
1270		- if (c0 > time * rps->power.up_threshold)
1271		- events = GEN6_PM_RP_UP_THRESHOLD;
1272		- else if (c0 < time * rps->power.down_threshold)
1273		- events = GEN6_PM_RP_DOWN_THRESHOLD;
1274		- }
1275		-
1276		- rps->ei = now;
1277		- return events;
1278		-}
1279		-
1280		-static void gen6_pm_rps_work(struct work_struct *work)
1281		-{
1282		- struct drm_i915_private *dev_priv =
1283		- container_of(work, struct drm_i915_private, gt_pm.rps.work);
1284		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
1285		- bool client_boost = false;
1286		- int new_delay, adj, min, max;
1287		- u32 pm_iir = 0;
1288		-
1289		- spin_lock_irq(&dev_priv->irq_lock);
1290		- if (rps->interrupts_enabled) {
1291		- pm_iir = fetch_and_zero(&rps->pm_iir);
1292		- client_boost = atomic_read(&rps->num_waiters);
1293		- }
1294		- spin_unlock_irq(&dev_priv->irq_lock);
1295		-
1296		- /* Make sure we didn't queue anything we're not going to process. */
1297		- WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1298		- if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1299		- goto out;
1300		-
1301		- mutex_lock(&dev_priv->pcu_lock);
1302		-
1303		- pm_iir \|= vlv_wa_c0_ei(dev_priv, pm_iir);
1304		-
1305		- adj = rps->last_adj;
1306		- new_delay = rps->cur_freq;
1307		- min = rps->min_freq_softlimit;
1308		- max = rps->max_freq_softlimit;
1309		- if (client_boost)
1310		- max = rps->max_freq;
1311		- if (client_boost && new_delay < rps->boost_freq) {
1312		- new_delay = rps->boost_freq;
1313		- adj = 0;
1314		- } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1315		- if (adj > 0)
1316		- adj *= 2;
1317		- else /* CHV needs even encode values */
1318		- adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1319		-
1320		- if (new_delay >= rps->max_freq_softlimit)
1321		- adj = 0;
1322		- } else if (client_boost) {
1323		- adj = 0;
1324		- } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1325		- if (rps->cur_freq > rps->efficient_freq)
1326		- new_delay = rps->efficient_freq;
1327		- else if (rps->cur_freq > rps->min_freq_softlimit)
1328		- new_delay = rps->min_freq_softlimit;
1329		- adj = 0;
1330		- } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1331		- if (adj < 0)
1332		- adj *= 2;
1333		- else /* CHV needs even encode values */
1334		- adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1335		-
1336		- if (new_delay <= rps->min_freq_softlimit)
1337		- adj = 0;
1338		- } else { /* unknown event */
1339		- adj = 0;
1340		- }
1341		-
1342		- rps->last_adj = adj;
1343		-
1344		- /* sysfs frequency interfaces may have snuck in while servicing the
1345		- * interrupt
1346		- */
1347		- new_delay += adj;
1348		- new_delay = clamp_t(int, new_delay, min, max);
1349		-
1350		- if (intel_set_rps(dev_priv, new_delay)) {
1351		- DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1352		- rps->last_adj = 0;
1353		- }
1354		-
1355		- mutex_unlock(&dev_priv->pcu_lock);
1356		-
1357		-out:
1358		- /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1359		- spin_lock_irq(&dev_priv->irq_lock);
1360		- if (rps->interrupts_enabled)
1361		- gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1362		- spin_unlock_irq(&dev_priv->irq_lock);
1363		-}
1364		-
1365		-
1366	947	/**
1367		- * ivybridge_parity_work - Workqueue called when a parity error interrupt
	948	+ * ivb_parity_work - Workqueue called when a parity error interrupt
1368	949	* occurred.
1369	950	* @work: workqueue struct
1370	951	*
..	..	@@ -1372,14 +953,15 @@
1372	953	* this event, userspace should try to remap the bad rows since statistically
1373	954	* it is likely the same row is more likely to go bad again.
1374	955	*/
1375		-static void ivybridge_parity_work(struct work_struct *work)
	956	+static void ivb_parity_work(struct work_struct *work)
1376	957	{
1377	958	struct drm_i915_private *dev_priv =
1378	959	container_of(work, typeof(*dev_priv), l3_parity.error_work);
	960	+ struct intel_gt *gt = &dev_priv->gt;
1379	961	u32 error_status, row, bank, subbank;
1380	962	char *parity_event[6];
1381		- uint32_t misccpctl;
1382		- uint8_t slice = 0;
	963	+ u32 misccpctl;
	964	+ u8 slice = 0;
1383	965
1384	966	/* We must turn off DOP level clock gating to access the L3 registers.
1385	967	* In order to prevent a get/put style interface, acquire struct mutex
..	..	@@ -1388,7 +970,7 @@
1388	970	mutex_lock(&dev_priv->drm.struct_mutex);
1389	971
1390	972	/* If we've screwed up tracking, just let the interrupt fire again */
1391		- if (WARN_ON(!dev_priv->l3_parity.which_slice))
	973	+ if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
1392	974	goto out;
1393	975
1394	976	misccpctl = I915_READ(GEN7_MISCCPCTL);
..	..	@@ -1399,7 +981,8 @@
1399	981	i915_reg_t reg;
1400	982
1401	983	slice--;
1402		- if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
	984	+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
	985	+ slice >= NUM_L3_SLICES(dev_priv)))
1403	986	break;
1404	987
1405	988	dev_priv->l3_parity.which_slice &= ~(1<<slice);
..	..	@@ -1436,159 +1019,29 @@
1436	1019	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1437	1020
1438	1021	out:
1439		- WARN_ON(dev_priv->l3_parity.which_slice);
1440		- spin_lock_irq(&dev_priv->irq_lock);
1441		- gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1442		- spin_unlock_irq(&dev_priv->irq_lock);
	1022	+ drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
	1023	+ spin_lock_irq(&gt->irq_lock);
	1024	+ gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
	1025	+ spin_unlock_irq(&gt->irq_lock);
1443	1026
1444	1027	mutex_unlock(&dev_priv->drm.struct_mutex);
1445		-}
1446		-
1447		-static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1448		- u32 iir)
1449		-{
1450		- if (!HAS_L3_DPF(dev_priv))
1451		- return;
1452		-
1453		- spin_lock(&dev_priv->irq_lock);
1454		- gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1455		- spin_unlock(&dev_priv->irq_lock);
1456		-
1457		- iir &= GT_PARITY_ERROR(dev_priv);
1458		- if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1459		- dev_priv->l3_parity.which_slice \|= 1 << 1;
1460		-
1461		- if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1462		- dev_priv->l3_parity.which_slice \|= 1 << 0;
1463		-
1464		- queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1465		-}
1466		-
1467		-static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1468		- u32 gt_iir)
1469		-{
1470		- if (gt_iir & GT_RENDER_USER_INTERRUPT)
1471		- notify_ring(dev_priv->engine[RCS]);
1472		- if (gt_iir & ILK_BSD_USER_INTERRUPT)
1473		- notify_ring(dev_priv->engine[VCS]);
1474		-}
1475		-
1476		-static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1477		- u32 gt_iir)
1478		-{
1479		- if (gt_iir & GT_RENDER_USER_INTERRUPT)
1480		- notify_ring(dev_priv->engine[RCS]);
1481		- if (gt_iir & GT_BSD_USER_INTERRUPT)
1482		- notify_ring(dev_priv->engine[VCS]);
1483		- if (gt_iir & GT_BLT_USER_INTERRUPT)
1484		- notify_ring(dev_priv->engine[BCS]);
1485		-
1486		- if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT \|
1487		- GT_BSD_CS_ERROR_INTERRUPT \|
1488		- GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1489		- DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1490		-
1491		- if (gt_iir & GT_PARITY_ERROR(dev_priv))
1492		- ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1493		-}
1494		-
1495		-static void
1496		-gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1497		-{
1498		- bool tasklet = false;
1499		-
1500		- if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
1501		- tasklet = true;
1502		-
1503		- if (iir & GT_RENDER_USER_INTERRUPT) {
1504		- notify_ring(engine);
1505		- tasklet \|= USES_GUC_SUBMISSION(engine->i915);
1506		- }
1507		-
1508		- if (tasklet)
1509		- tasklet_hi_schedule(&engine->execlists.tasklet);
1510		-}
1511		-
1512		-static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1513		- u32 master_ctl, u32 gt_iir[4])
1514		-{
1515		- void __iomem * const regs = i915->regs;
1516		-
1517		-#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ \| \
1518		- GEN8_GT_BCS_IRQ \| \
1519		- GEN8_GT_VCS1_IRQ \| \
1520		- GEN8_GT_VCS2_IRQ \| \
1521		- GEN8_GT_VECS_IRQ \| \
1522		- GEN8_GT_PM_IRQ \| \
1523		- GEN8_GT_GUC_IRQ)
1524		-
1525		- if (master_ctl & (GEN8_GT_RCS_IRQ \| GEN8_GT_BCS_IRQ)) {
1526		- gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1527		- if (likely(gt_iir[0]))
1528		- raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1529		- }
1530		-
1531		- if (master_ctl & (GEN8_GT_VCS1_IRQ \| GEN8_GT_VCS2_IRQ)) {
1532		- gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1533		- if (likely(gt_iir[1]))
1534		- raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1535		- }
1536		-
1537		- if (master_ctl & (GEN8_GT_PM_IRQ \| GEN8_GT_GUC_IRQ)) {
1538		- gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1539		- if (likely(gt_iir[2] & (i915->pm_rps_events \|
1540		- i915->pm_guc_events)))
1541		- raw_reg_write(regs, GEN8_GT_IIR(2),
1542		- gt_iir[2] & (i915->pm_rps_events \|
1543		- i915->pm_guc_events));
1544		- }
1545		-
1546		- if (master_ctl & GEN8_GT_VECS_IRQ) {
1547		- gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1548		- if (likely(gt_iir[3]))
1549		- raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1550		- }
1551		-}
1552		-
1553		-static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1554		- u32 master_ctl, u32 gt_iir[4])
1555		-{
1556		- if (master_ctl & (GEN8_GT_RCS_IRQ \| GEN8_GT_BCS_IRQ)) {
1557		- gen8_cs_irq_handler(i915->engine[RCS],
1558		- gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1559		- gen8_cs_irq_handler(i915->engine[BCS],
1560		- gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1561		- }
1562		-
1563		- if (master_ctl & (GEN8_GT_VCS1_IRQ \| GEN8_GT_VCS2_IRQ)) {
1564		- gen8_cs_irq_handler(i915->engine[VCS],
1565		- gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1566		- gen8_cs_irq_handler(i915->engine[VCS2],
1567		- gt_iir[1] >> GEN8_VCS2_IRQ_SHIFT);
1568		- }
1569		-
1570		- if (master_ctl & GEN8_GT_VECS_IRQ) {
1571		- gen8_cs_irq_handler(i915->engine[VECS],
1572		- gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1573		- }
1574		-
1575		- if (master_ctl & (GEN8_GT_PM_IRQ \| GEN8_GT_GUC_IRQ)) {
1576		- gen6_rps_irq_handler(i915, gt_iir[2]);
1577		- gen9_guc_irq_handler(i915, gt_iir[2]);
1578		- }
1579	1028	}
1580	1029
1581	1030	static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1582	1031	{
1583	1032	switch (pin) {
1584		- case HPD_PORT_C:
	1033	+ case HPD_PORT_TC1:
1585	1034	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1586		- case HPD_PORT_D:
	1035	+ case HPD_PORT_TC2:
1587	1036	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1588		- case HPD_PORT_E:
	1037	+ case HPD_PORT_TC3:
1589	1038	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1590		- case HPD_PORT_F:
	1039	+ case HPD_PORT_TC4:
1591	1040	return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
	1041	+ case HPD_PORT_TC5:
	1042	+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
	1043	+ case HPD_PORT_TC6:
	1044	+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1592	1045	default:
1593	1046	return false;
1594	1047	}
..	..	@@ -1612,9 +1065,11 @@
1612	1065	{
1613	1066	switch (pin) {
1614	1067	case HPD_PORT_A:
1615		- return val & ICP_DDIA_HPD_LONG_DETECT;
	1068	+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1616	1069	case HPD_PORT_B:
1617		- return val & ICP_DDIB_HPD_LONG_DETECT;
	1070	+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
	1071	+ case HPD_PORT_C:
	1072	+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1618	1073	default:
1619	1074	return false;
1620	1075	}
..	..	@@ -1623,14 +1078,18 @@
1623	1078	static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1624	1079	{
1625	1080	switch (pin) {
1626		- case HPD_PORT_C:
	1081	+ case HPD_PORT_TC1:
1627	1082	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1628		- case HPD_PORT_D:
	1083	+ case HPD_PORT_TC2:
1629	1084	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1630		- case HPD_PORT_E:
	1085	+ case HPD_PORT_TC3:
1631	1086	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1632		- case HPD_PORT_F:
	1087	+ case HPD_PORT_TC4:
1633	1088	return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
	1089	+ case HPD_PORT_TC5:
	1090	+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
	1091	+ case HPD_PORT_TC6:
	1092	+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1634	1093	default:
1635	1094	return false;
1636	1095	}
..	..	@@ -1715,6 +1174,8 @@
1715	1174	{
1716	1175	enum hpd_pin pin;
1717	1176
	1177	+ BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
	1178	+
1718	1179	for_each_hpd_pin(pin) {
1719	1180	if ((hpd[pin] & hotplug_trigger) == 0)
1720	1181	continue;
..	..	@@ -1725,8 +1186,9 @@
1725	1186	*long_mask \|= BIT(pin);
1726	1187	}
1727	1188
1728		- DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1729		- hotplug_trigger, dig_hotplug_reg, pin_mask, long_mask);
	1189	+ drm_dbg(&dev_priv->drm,
	1190	+ "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
	1191	+ hotplug_trigger, dig_hotplug_reg, pin_mask, long_mask);
1730	1192
1731	1193	}
1732	1194
..	..	@@ -1743,13 +1205,15 @@
1743	1205	#if defined(CONFIG_DEBUG_FS)
1744	1206	static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1745	1207	enum pipe pipe,
1746		- uint32_t crc0, uint32_t crc1,
1747		- uint32_t crc2, uint32_t crc3,
1748		- uint32_t crc4)
	1208	+ u32 crc0, u32 crc1,
	1209	+ u32 crc2, u32 crc3,
	1210	+ u32 crc4)
1749	1211	{
1750		- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1751	1212	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1752		- uint32_t crcs[5];
	1213	+ struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
	1214	+ u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
	1215	+
	1216	+ trace_intel_pipe_crc(crtc, crcs);
1753	1217
1754	1218	spin_lock(&pipe_crc->lock);
1755	1219	/*
..	..	@@ -1768,11 +1232,6 @@
1768	1232	}
1769	1233	spin_unlock(&pipe_crc->lock);
1770	1234
1771		- crcs[0] = crc0;
1772		- crcs[1] = crc1;
1773		- crcs[2] = crc2;
1774		- crcs[3] = crc3;
1775		- crcs[4] = crc4;
1776	1235	drm_crtc_add_crc_entry(&crtc->base, true,
1777	1236	drm_crtc_accurate_vblank_count(&crtc->base),
1778	1237	crcs);
..	..	@@ -1781,9 +1240,9 @@
1781	1240	static inline void
1782	1241	display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1783	1242	enum pipe pipe,
1784		- uint32_t crc0, uint32_t crc1,
1785		- uint32_t crc2, uint32_t crc3,
1786		- uint32_t crc4) {}
	1243	+ u32 crc0, u32 crc1,
	1244	+ u32 crc2, u32 crc3,
	1245	+ u32 crc4) {}
1787	1246	#endif
1788	1247
1789	1248
..	..	@@ -1809,7 +1268,7 @@
1809	1268	static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1810	1269	enum pipe pipe)
1811	1270	{
1812		- uint32_t res1, res2;
	1271	+ u32 res1, res2;
1813	1272
1814	1273	if (INTEL_GEN(dev_priv) >= 3)
1815	1274	res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
..	..	@@ -1828,41 +1287,6 @@
1828	1287	res1, res2);
1829	1288	}
1830	1289
1831		-/* The RPS events need forcewake, so we add them to a work queue and mask their
1832		- * IMR bits until the work is done. Other interrupts can be processed without
1833		- * the work queue. */
1834		-static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1835		-{
1836		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
1837		-
1838		- if (pm_iir & dev_priv->pm_rps_events) {
1839		- spin_lock(&dev_priv->irq_lock);
1840		- gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1841		- if (rps->interrupts_enabled) {
1842		- rps->pm_iir \|= pm_iir & dev_priv->pm_rps_events;
1843		- schedule_work(&rps->work);
1844		- }
1845		- spin_unlock(&dev_priv->irq_lock);
1846		- }
1847		-
1848		- if (INTEL_GEN(dev_priv) >= 8)
1849		- return;
1850		-
1851		- if (HAS_VEBOX(dev_priv)) {
1852		- if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1853		- notify_ring(dev_priv->engine[VECS]);
1854		-
1855		- if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1856		- DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1857		- }
1858		-}
1859		-
1860		-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1861		-{
1862		- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1863		- intel_guc_to_host_event_handler(&dev_priv->guc);
1864		-}
1865		-
1866	1290	static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1867	1291	{
1868	1292	enum pipe pipe;
..	..	@@ -1879,7 +1303,7 @@
1879	1303	static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1880	1304	u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1881	1305	{
1882		- int pipe;
	1306	+ enum pipe pipe;
1883	1307
1884	1308	spin_lock(&dev_priv->irq_lock);
1885	1309
..	..	@@ -1904,6 +1328,7 @@
1904	1328	status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1905	1329
1906	1330	switch (pipe) {
	1331	+ default:
1907	1332	case PIPE_A:
1908	1333	iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1909	1334	break;
..	..	@@ -1948,7 +1373,7 @@
1948	1373
1949	1374	for_each_pipe(dev_priv, pipe) {
1950	1375	if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1951		- drm_handle_vblank(&dev_priv->drm, pipe);
	1376	+ intel_handle_vblank(dev_priv, pipe);
1952	1377
1953	1378	if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1954	1379	i9xx_pipe_crc_irq_handler(dev_priv, pipe);
..	..	@@ -1966,7 +1391,7 @@
1966	1391
1967	1392	for_each_pipe(dev_priv, pipe) {
1968	1393	if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1969		- drm_handle_vblank(&dev_priv->drm, pipe);
	1394	+ intel_handle_vblank(dev_priv, pipe);
1970	1395
1971	1396	if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1972	1397	blc_event = true;
..	..	@@ -1990,7 +1415,7 @@
1990	1415
1991	1416	for_each_pipe(dev_priv, pipe) {
1992	1417	if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1993		- drm_handle_vblank(&dev_priv->drm, pipe);
	1418	+ intel_handle_vblank(dev_priv, pipe);
1994	1419
1995	1420	if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1996	1421	blc_event = true;
..	..	@@ -2016,7 +1441,7 @@
2016	1441
2017	1442	for_each_pipe(dev_priv, pipe) {
2018	1443	if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2019		- drm_handle_vblank(&dev_priv->drm, pipe);
	1444	+ intel_handle_vblank(dev_priv, pipe);
2020	1445
2021	1446	if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2022	1447	i9xx_pipe_crc_irq_handler(dev_priv, pipe);
..	..	@@ -2060,9 +1485,9 @@
2060	1485	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2061	1486	}
2062	1487
2063		- WARN_ONCE(1,
2064		- "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
2065		- I915_READ(PORT_HOTPLUG_STAT));
	1488	+ drm_WARN_ONCE(&dev_priv->drm, 1,
	1489	+ "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
	1490	+ I915_READ(PORT_HOTPLUG_STAT));
2066	1491
2067	1492	return hotplug_status;
2068	1493	}
..	..	@@ -2071,46 +1496,39 @@
2071	1496	u32 hotplug_status)
2072	1497	{
2073	1498	u32 pin_mask = 0, long_mask = 0;
	1499	+ u32 hotplug_trigger;
2074	1500
2075		- if (IS_G4X(dev_priv) \|\| IS_VALLEYVIEW(dev_priv) \|\|
2076		- IS_CHERRYVIEW(dev_priv)) {
2077		- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
	1501	+ if (IS_G4X(dev_priv) \|\|
	1502	+ IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
	1503	+ hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
	1504	+ else
	1505	+ hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2078	1506
2079		- if (hotplug_trigger) {
2080		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2081		- hotplug_trigger, hotplug_trigger,
2082		- hpd_status_g4x,
2083		- i9xx_port_hotplug_long_detect);
	1507	+ if (hotplug_trigger) {
	1508	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	1509	+ hotplug_trigger, hotplug_trigger,
	1510	+ dev_priv->hotplug.hpd,
	1511	+ i9xx_port_hotplug_long_detect);
2084	1512
2085		- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2086		- }
2087		-
2088		- if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2089		- dp_aux_irq_handler(dev_priv);
2090		- } else {
2091		- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2092		-
2093		- if (hotplug_trigger) {
2094		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2095		- hotplug_trigger, hotplug_trigger,
2096		- hpd_status_i915,
2097		- i9xx_port_hotplug_long_detect);
2098		- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2099		- }
	1513	+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2100	1514	}
	1515	+
	1516	+ if ((IS_G4X(dev_priv) \|\|
	1517	+ IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv)) &&
	1518	+ hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
	1519	+ dp_aux_irq_handler(dev_priv);
2101	1520	}
2102	1521
2103	1522	static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2104	1523	{
2105		- struct drm_device *dev = arg;
2106		- struct drm_i915_private *dev_priv = to_i915(dev);
	1524	+ struct drm_i915_private *dev_priv = arg;
2107	1525	irqreturn_t ret = IRQ_NONE;
2108	1526
2109	1527	if (!intel_irqs_enabled(dev_priv))
2110	1528	return IRQ_NONE;
2111	1529
2112	1530	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2113		- disable_rpm_wakeref_asserts(dev_priv);
	1531	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2114	1532
2115	1533	do {
2116	1534	u32 iir, gt_iir, pm_iir;
..	..	@@ -2171,9 +1589,9 @@
2171	1589	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2172	1590
2173	1591	if (gt_iir)
2174		- snb_gt_irq_handler(dev_priv, gt_iir);
	1592	+ gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2175	1593	if (pm_iir)
2176		- gen6_rps_irq_handler(dev_priv, pm_iir);
	1594	+ gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
2177	1595
2178	1596	if (hotplug_status)
2179	1597	i9xx_hpd_irq_handler(dev_priv, hotplug_status);
..	..	@@ -2181,28 +1599,26 @@
2181	1599	valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2182	1600	} while (0);
2183	1601
2184		- enable_rpm_wakeref_asserts(dev_priv);
	1602	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2185	1603
2186	1604	return ret;
2187	1605	}
2188	1606
2189	1607	static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2190	1608	{
2191		- struct drm_device *dev = arg;
2192		- struct drm_i915_private *dev_priv = to_i915(dev);
	1609	+ struct drm_i915_private *dev_priv = arg;
2193	1610	irqreturn_t ret = IRQ_NONE;
2194	1611
2195	1612	if (!intel_irqs_enabled(dev_priv))
2196	1613	return IRQ_NONE;
2197	1614
2198	1615	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2199		- disable_rpm_wakeref_asserts(dev_priv);
	1616	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2200	1617
2201	1618	do {
2202	1619	u32 master_ctl, iir;
2203	1620	u32 pipe_stats[I915_MAX_PIPES] = {};
2204	1621	u32 hotplug_status = 0;
2205		- u32 gt_iir[4];
2206	1622	u32 ier = 0;
2207	1623
2208	1624	master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
..	..	@@ -2230,7 +1646,7 @@
2230	1646	ier = I915_READ(VLV_IER);
2231	1647	I915_WRITE(VLV_IER, 0);
2232	1648
2233		- gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
	1649	+ gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2234	1650
2235	1651	if (iir & I915_DISPLAY_PORT_INTERRUPT)
2236	1652	hotplug_status = i9xx_hpd_irq_ack(dev_priv);
..	..	@@ -2254,22 +1670,19 @@
2254	1670	I915_WRITE(VLV_IER, ier);
2255	1671	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2256	1672
2257		- gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2258		-
2259	1673	if (hotplug_status)
2260	1674	i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2261	1675
2262	1676	valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2263	1677	} while (0);
2264	1678
2265		- enable_rpm_wakeref_asserts(dev_priv);
	1679	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2266	1680
2267	1681	return ret;
2268	1682	}
2269	1683
2270	1684	static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2271		- u32 hotplug_trigger,
2272		- const u32 hpd[HPD_NUM_PINS])
	1685	+ u32 hotplug_trigger)
2273	1686	{
2274	1687	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2275	1688
..	..	@@ -2292,8 +1705,9 @@
2292	1705	if (!hotplug_trigger)
2293	1706	return;
2294	1707
2295		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2296		- dig_hotplug_reg, hpd,
	1708	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	1709	+ hotplug_trigger, dig_hotplug_reg,
	1710	+ dev_priv->hotplug.pch_hpd,
2297	1711	pch_port_hotplug_long_detect);
2298	1712
2299	1713	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
..	..	@@ -2301,16 +1715,16 @@
2301	1715
2302	1716	static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2303	1717	{
2304		- int pipe;
	1718	+ enum pipe pipe;
2305	1719	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2306	1720
2307		- ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
	1721	+ ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
2308	1722
2309	1723	if (pch_iir & SDE_AUDIO_POWER_MASK) {
2310	1724	int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2311	1725	SDE_AUDIO_POWER_SHIFT);
2312		- DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2313		- port_name(port));
	1726	+ drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
	1727	+ port_name(port));
2314	1728	}
2315	1729
2316	1730	if (pch_iir & SDE_AUX_MASK)
..	..	@@ -2320,25 +1734,27 @@
2320	1734	gmbus_irq_handler(dev_priv);
2321	1735
2322	1736	if (pch_iir & SDE_AUDIO_HDCP_MASK)
2323		- DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
	1737	+ drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
2324	1738
2325	1739	if (pch_iir & SDE_AUDIO_TRANS_MASK)
2326		- DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
	1740	+ drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
2327	1741
2328	1742	if (pch_iir & SDE_POISON)
2329		- DRM_ERROR("PCH poison interrupt\n");
	1743	+ drm_err(&dev_priv->drm, "PCH poison interrupt\n");
2330	1744
2331		- if (pch_iir & SDE_FDI_MASK)
	1745	+ if (pch_iir & SDE_FDI_MASK) {
2332	1746	for_each_pipe(dev_priv, pipe)
2333		- DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2334		- pipe_name(pipe),
2335		- I915_READ(FDI_RX_IIR(pipe)));
	1747	+ drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
	1748	+ pipe_name(pipe),
	1749	+ I915_READ(FDI_RX_IIR(pipe)));
	1750	+ }
2336	1751
2337	1752	if (pch_iir & (SDE_TRANSB_CRC_DONE \| SDE_TRANSA_CRC_DONE))
2338		- DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
	1753	+ drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
2339	1754
2340	1755	if (pch_iir & (SDE_TRANSB_CRC_ERR \| SDE_TRANSA_CRC_ERR))
2341		- DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
	1756	+ drm_dbg(&dev_priv->drm,
	1757	+ "PCH transcoder CRC error interrupt\n");
2342	1758
2343	1759	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2344	1760	intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
..	..	@@ -2353,7 +1769,7 @@
2353	1769	enum pipe pipe;
2354	1770
2355	1771	if (err_int & ERR_INT_POISON)
2356		- DRM_ERROR("Poison interrupt\n");
	1772	+ drm_err(&dev_priv->drm, "Poison interrupt\n");
2357	1773
2358	1774	for_each_pipe(dev_priv, pipe) {
2359	1775	if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
..	..	@@ -2376,7 +1792,7 @@
2376	1792	enum pipe pipe;
2377	1793
2378	1794	if (serr_int & SERR_INT_POISON)
2379		- DRM_ERROR("PCH poison interrupt\n");
	1795	+ drm_err(&dev_priv->drm, "PCH poison interrupt\n");
2380	1796
2381	1797	for_each_pipe(dev_priv, pipe)
2382	1798	if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
..	..	@@ -2387,16 +1803,16 @@
2387	1803
2388	1804	static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2389	1805	{
2390		- int pipe;
	1806	+ enum pipe pipe;
2391	1807	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2392	1808
2393		- ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
	1809	+ ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
2394	1810
2395	1811	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2396	1812	int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2397	1813	SDE_AUDIO_POWER_SHIFT_CPT);
2398		- DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2399		- port_name(port));
	1814	+ drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
	1815	+ port_name(port));
2400	1816	}
2401	1817
2402	1818	if (pch_iir & SDE_AUX_MASK_CPT)
..	..	@@ -2406,16 +1822,17 @@
2406	1822	gmbus_irq_handler(dev_priv);
2407	1823
2408	1824	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2409		- DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
	1825	+ drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
2410	1826
2411	1827	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2412		- DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
	1828	+ drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
2413	1829
2414		- if (pch_iir & SDE_FDI_MASK_CPT)
	1830	+ if (pch_iir & SDE_FDI_MASK_CPT) {
2415	1831	for_each_pipe(dev_priv, pipe)
2416		- DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2417		- pipe_name(pipe),
2418		- I915_READ(FDI_RX_IIR(pipe)));
	1832	+ drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
	1833	+ pipe_name(pipe),
	1834	+ I915_READ(FDI_RX_IIR(pipe)));
	1835	+ }
2419	1836
2420	1837	if (pch_iir & SDE_ERROR_CPT)
2421	1838	cpt_serr_int_handler(dev_priv);
..	..	@@ -2423,9 +1840,26 @@
2423	1840
2424	1841	static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2425	1842	{
2426		- u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2427		- u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
	1843	+ u32 ddi_hotplug_trigger, tc_hotplug_trigger;
2428	1844	u32 pin_mask = 0, long_mask = 0;
	1845	+
	1846	+ if (HAS_PCH_TGP(dev_priv)) {
	1847	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
	1848	+ tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
	1849	+ } else if (HAS_PCH_JSP(dev_priv)) {
	1850	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
	1851	+ tc_hotplug_trigger = 0;
	1852	+ } else if (HAS_PCH_MCC(dev_priv)) {
	1853	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
	1854	+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
	1855	+ } else {
	1856	+ drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
	1857	+ "Unrecognized PCH type 0x%x\n",
	1858	+ INTEL_PCH_TYPE(dev_priv));
	1859	+
	1860	+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
	1861	+ tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
	1862	+ }
2429	1863
2430	1864	if (ddi_hotplug_trigger) {
2431	1865	u32 dig_hotplug_reg;
..	..	@@ -2434,8 +1868,8 @@
2434	1868	I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2435	1869
2436	1870	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2437		- ddi_hotplug_trigger,
2438		- dig_hotplug_reg, hpd_icp,
	1871	+ ddi_hotplug_trigger, dig_hotplug_reg,
	1872	+ dev_priv->hotplug.pch_hpd,
2439	1873	icp_ddi_port_hotplug_long_detect);
2440	1874	}
2441	1875
..	..	@@ -2446,8 +1880,8 @@
2446	1880	I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2447	1881
2448	1882	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2449		- tc_hotplug_trigger,
2450		- dig_hotplug_reg, hpd_icp,
	1883	+ tc_hotplug_trigger, dig_hotplug_reg,
	1884	+ dev_priv->hotplug.pch_hpd,
2451	1885	icp_tc_port_hotplug_long_detect);
2452	1886	}
2453	1887
..	..	@@ -2472,7 +1906,8 @@
2472	1906	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2473	1907
2474	1908	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2475		- hotplug_trigger, dig_hotplug_reg, hpd_spt,
	1909	+ hotplug_trigger, dig_hotplug_reg,
	1910	+ dev_priv->hotplug.pch_hpd,
2476	1911	spt_port_hotplug_long_detect);
2477	1912	}
2478	1913
..	..	@@ -2483,7 +1918,8 @@
2483	1918	I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2484	1919
2485	1920	intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2486		- hotplug2_trigger, dig_hotplug_reg, hpd_spt,
	1921	+ hotplug2_trigger, dig_hotplug_reg,
	1922	+ dev_priv->hotplug.pch_hpd,
2487	1923	spt_port_hotplug2_long_detect);
2488	1924	}
2489	1925
..	..	@@ -2495,16 +1931,16 @@
2495	1931	}
2496	1932
2497	1933	static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2498		- u32 hotplug_trigger,
2499		- const u32 hpd[HPD_NUM_PINS])
	1934	+ u32 hotplug_trigger)
2500	1935	{
2501	1936	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2502	1937
2503	1938	dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2504	1939	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2505	1940
2506		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2507		- dig_hotplug_reg, hpd,
	1941	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	1942	+ hotplug_trigger, dig_hotplug_reg,
	1943	+ dev_priv->hotplug.hpd,
2508	1944	ilk_port_hotplug_long_detect);
2509	1945
2510	1946	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
..	..	@@ -2517,7 +1953,7 @@
2517	1953	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2518	1954
2519	1955	if (hotplug_trigger)
2520		- ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
	1956	+ ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2521	1957
2522	1958	if (de_iir & DE_AUX_CHANNEL_A)
2523	1959	dp_aux_irq_handler(dev_priv);
..	..	@@ -2526,11 +1962,11 @@
2526	1962	intel_opregion_asle_intr(dev_priv);
2527	1963
2528	1964	if (de_iir & DE_POISON)
2529		- DRM_ERROR("Poison interrupt\n");
	1965	+ drm_err(&dev_priv->drm, "Poison interrupt\n");
2530	1966
2531	1967	for_each_pipe(dev_priv, pipe) {
2532	1968	if (de_iir & DE_PIPE_VBLANK(pipe))
2533		- drm_handle_vblank(&dev_priv->drm, pipe);
	1969	+ intel_handle_vblank(dev_priv, pipe);
2534	1970
2535	1971	if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2536	1972	intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
..	..	@@ -2552,8 +1988,8 @@
2552	1988	I915_WRITE(SDEIIR, pch_iir);
2553	1989	}
2554	1990
2555		- if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2556		- ironlake_rps_change_irq_handler(dev_priv);
	1991	+ if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
	1992	+ gen5_rps_irq_handler(&dev_priv->gt.rps);
2557	1993	}
2558	1994
2559	1995	static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
..	..	@@ -2563,7 +1999,7 @@
2563	1999	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2564	2000
2565	2001	if (hotplug_trigger)
2566		- ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
	2002	+ ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2567	2003
2568	2004	if (de_iir & DE_ERR_INT_IVB)
2569	2005	ivb_err_int_handler(dev_priv);
..	..	@@ -2583,7 +2019,7 @@
2583	2019
2584	2020	for_each_pipe(dev_priv, pipe) {
2585	2021	if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2586		- drm_handle_vblank(&dev_priv->drm, pipe);
	2022	+ intel_handle_vblank(dev_priv, pipe);
2587	2023	}
2588	2024
2589	2025	/* check event from PCH */
..	..	@@ -2605,85 +2041,85 @@
2605	2041	* 4 - Process the interrupt(s) that had bits set in the IIRs.
2606	2042	* 5 - Re-enable Master Interrupt Control.
2607	2043	*/
2608		-static irqreturn_t ironlake_irq_handler(int irq, void *arg)
	2044	+static irqreturn_t ilk_irq_handler(int irq, void *arg)
2609	2045	{
2610		- struct drm_device *dev = arg;
2611		- struct drm_i915_private *dev_priv = to_i915(dev);
	2046	+ struct drm_i915_private *i915 = arg;
	2047	+ void __iomem * const regs = i915->uncore.regs;
2612	2048	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2613	2049	irqreturn_t ret = IRQ_NONE;
2614	2050
2615		- if (!intel_irqs_enabled(dev_priv))
	2051	+ if (unlikely(!intel_irqs_enabled(i915)))
2616	2052	return IRQ_NONE;
2617	2053
2618	2054	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2619		- disable_rpm_wakeref_asserts(dev_priv);
	2055	+ disable_rpm_wakeref_asserts(&i915->runtime_pm);
2620	2056
2621	2057	/* disable master interrupt before clearing iir */
2622		- de_ier = I915_READ(DEIER);
2623		- I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
	2058	+ de_ier = raw_reg_read(regs, DEIER);
	2059	+ raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2624	2060
2625	2061	/* Disable south interrupts. We'll only write to SDEIIR once, so further
2626	2062	* interrupts will will be stored on its back queue, and then we'll be
2627	2063	* able to process them after we restore SDEIER (as soon as we restore
2628	2064	* it, we'll get an interrupt if SDEIIR still has something to process
2629	2065	* due to its back queue). */
2630		- if (!HAS_PCH_NOP(dev_priv)) {
2631		- sde_ier = I915_READ(SDEIER);
2632		- I915_WRITE(SDEIER, 0);
	2066	+ if (!HAS_PCH_NOP(i915)) {
	2067	+ sde_ier = raw_reg_read(regs, SDEIER);
	2068	+ raw_reg_write(regs, SDEIER, 0);
2633	2069	}
2634	2070
2635	2071	/* Find, clear, then process each source of interrupt */
2636	2072
2637		- gt_iir = I915_READ(GTIIR);
	2073	+ gt_iir = raw_reg_read(regs, GTIIR);
2638	2074	if (gt_iir) {
2639		- I915_WRITE(GTIIR, gt_iir);
2640		- ret = IRQ_HANDLED;
2641		- if (INTEL_GEN(dev_priv) >= 6)
2642		- snb_gt_irq_handler(dev_priv, gt_iir);
	2075	+ raw_reg_write(regs, GTIIR, gt_iir);
	2076	+ if (INTEL_GEN(i915) >= 6)
	2077	+ gen6_gt_irq_handler(&i915->gt, gt_iir);
2643	2078	else
2644		- ilk_gt_irq_handler(dev_priv, gt_iir);
	2079	+ gen5_gt_irq_handler(&i915->gt, gt_iir);
	2080	+ ret = IRQ_HANDLED;
2645	2081	}
2646	2082
2647		- de_iir = I915_READ(DEIIR);
	2083	+ de_iir = raw_reg_read(regs, DEIIR);
2648	2084	if (de_iir) {
2649		- I915_WRITE(DEIIR, de_iir);
2650		- ret = IRQ_HANDLED;
2651		- if (INTEL_GEN(dev_priv) >= 7)
2652		- ivb_display_irq_handler(dev_priv, de_iir);
	2085	+ raw_reg_write(regs, DEIIR, de_iir);
	2086	+ if (INTEL_GEN(i915) >= 7)
	2087	+ ivb_display_irq_handler(i915, de_iir);
2653	2088	else
2654		- ilk_display_irq_handler(dev_priv, de_iir);
	2089	+ ilk_display_irq_handler(i915, de_iir);
	2090	+ ret = IRQ_HANDLED;
2655	2091	}
2656	2092
2657		- if (INTEL_GEN(dev_priv) >= 6) {
2658		- u32 pm_iir = I915_READ(GEN6_PMIIR);
	2093	+ if (INTEL_GEN(i915) >= 6) {
	2094	+ u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2659	2095	if (pm_iir) {
2660		- I915_WRITE(GEN6_PMIIR, pm_iir);
	2096	+ raw_reg_write(regs, GEN6_PMIIR, pm_iir);
	2097	+ gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2661	2098	ret = IRQ_HANDLED;
2662		- gen6_rps_irq_handler(dev_priv, pm_iir);
2663	2099	}
2664	2100	}
2665	2101
2666		- I915_WRITE(DEIER, de_ier);
2667		- if (!HAS_PCH_NOP(dev_priv))
2668		- I915_WRITE(SDEIER, sde_ier);
	2102	+ raw_reg_write(regs, DEIER, de_ier);
	2103	+ if (sde_ier)
	2104	+ raw_reg_write(regs, SDEIER, sde_ier);
2669	2105
2670	2106	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2671		- enable_rpm_wakeref_asserts(dev_priv);
	2107	+ enable_rpm_wakeref_asserts(&i915->runtime_pm);
2672	2108
2673	2109	return ret;
2674	2110	}
2675	2111
2676	2112	static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2677		- u32 hotplug_trigger,
2678		- const u32 hpd[HPD_NUM_PINS])
	2113	+ u32 hotplug_trigger)
2679	2114	{
2680	2115	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2681	2116
2682	2117	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2683	2118	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2684	2119
2685		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2686		- dig_hotplug_reg, hpd,
	2120	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	2121	+ hotplug_trigger, dig_hotplug_reg,
	2122	+ dev_priv->hotplug.hpd,
2687	2123	bxt_port_hotplug_long_detect);
2688	2124
2689	2125	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
..	..	@@ -2701,8 +2137,9 @@
2701	2137	dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2702	2138	I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2703	2139
2704		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2705		- dig_hotplug_reg, hpd_gen11,
	2140	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	2141	+ trigger_tc, dig_hotplug_reg,
	2142	+ dev_priv->hotplug.hpd,
2706	2143	gen11_port_hotplug_long_detect);
2707	2144	}
2708	2145
..	..	@@ -2712,15 +2149,92 @@
2712	2149	dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2713	2150	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2714	2151
2715		- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2716		- dig_hotplug_reg, hpd_gen11,
	2152	+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
	2153	+ trigger_tbt, dig_hotplug_reg,
	2154	+ dev_priv->hotplug.hpd,
2717	2155	gen11_port_hotplug_long_detect);
2718	2156	}
2719	2157
2720	2158	if (pin_mask)
2721	2159	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2722	2160	else
2723		- DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
	2161	+ drm_err(&dev_priv->drm,
	2162	+ "Unexpected DE HPD interrupt 0x%08x\n", iir);
	2163	+}
	2164	+
	2165	+static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
	2166	+{
	2167	+ u32 mask;
	2168	+
	2169	+ if (INTEL_GEN(dev_priv) >= 12)
	2170	+ return TGL_DE_PORT_AUX_DDIA \|
	2171	+ TGL_DE_PORT_AUX_DDIB \|
	2172	+ TGL_DE_PORT_AUX_DDIC \|
	2173	+ TGL_DE_PORT_AUX_USBC1 \|
	2174	+ TGL_DE_PORT_AUX_USBC2 \|
	2175	+ TGL_DE_PORT_AUX_USBC3 \|
	2176	+ TGL_DE_PORT_AUX_USBC4 \|
	2177	+ TGL_DE_PORT_AUX_USBC5 \|
	2178	+ TGL_DE_PORT_AUX_USBC6;
	2179	+
	2180	+
	2181	+ mask = GEN8_AUX_CHANNEL_A;
	2182	+ if (INTEL_GEN(dev_priv) >= 9)
	2183	+ mask \|= GEN9_AUX_CHANNEL_B \|
	2184	+ GEN9_AUX_CHANNEL_C \|
	2185	+ GEN9_AUX_CHANNEL_D;
	2186	+
	2187	+ if (IS_CNL_WITH_PORT_F(dev_priv) \|\| IS_GEN(dev_priv, 11))
	2188	+ mask \|= CNL_AUX_CHANNEL_F;
	2189	+
	2190	+ if (IS_GEN(dev_priv, 11))
	2191	+ mask \|= ICL_AUX_CHANNEL_E;
	2192	+
	2193	+ return mask;
	2194	+}
	2195	+
	2196	+static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
	2197	+{
	2198	+ if (IS_ROCKETLAKE(dev_priv))
	2199	+ return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
	2200	+ else if (INTEL_GEN(dev_priv) >= 11)
	2201	+ return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
	2202	+ else if (INTEL_GEN(dev_priv) >= 9)
	2203	+ return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
	2204	+ else
	2205	+ return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
	2206	+}
	2207	+
	2208	+static void
	2209	+gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
	2210	+{
	2211	+ bool found = false;
	2212	+
	2213	+ if (iir & GEN8_DE_MISC_GSE) {
	2214	+ intel_opregion_asle_intr(dev_priv);
	2215	+ found = true;
	2216	+ }
	2217	+
	2218	+ if (iir & GEN8_DE_EDP_PSR) {
	2219	+ u32 psr_iir;
	2220	+ i915_reg_t iir_reg;
	2221	+
	2222	+ if (INTEL_GEN(dev_priv) >= 12)
	2223	+ iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
	2224	+ else
	2225	+ iir_reg = EDP_PSR_IIR;
	2226	+
	2227	+ psr_iir = I915_READ(iir_reg);
	2228	+ I915_WRITE(iir_reg, psr_iir);
	2229	+
	2230	+ if (psr_iir)
	2231	+ found = true;
	2232	+
	2233	+ intel_psr_irq_handler(dev_priv, psr_iir);
	2234	+ }
	2235	+
	2236	+ if (!found)
	2237	+ drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2724	2238	}
2725	2239
2726	2240	static irqreturn_t
..	..	@@ -2733,29 +2247,13 @@
2733	2247	if (master_ctl & GEN8_DE_MISC_IRQ) {
2734	2248	iir = I915_READ(GEN8_DE_MISC_IIR);
2735	2249	if (iir) {
2736		- bool found = false;
2737		-
2738	2250	I915_WRITE(GEN8_DE_MISC_IIR, iir);
2739	2251	ret = IRQ_HANDLED;
2740		-
2741		- if (iir & GEN8_DE_MISC_GSE) {
2742		- intel_opregion_asle_intr(dev_priv);
2743		- found = true;
2744		- }
2745		-
2746		- if (iir & GEN8_DE_EDP_PSR) {
2747		- u32 psr_iir = I915_READ(EDP_PSR_IIR);
2748		-
2749		- intel_psr_irq_handler(dev_priv, psr_iir);
2750		- I915_WRITE(EDP_PSR_IIR, psr_iir);
2751		- found = true;
2752		- }
2753		-
2754		- if (!found)
2755		- DRM_ERROR("Unexpected DE Misc interrupt\n");
	2252	+ gen8_de_misc_irq_handler(dev_priv, iir);
	2253	+ } else {
	2254	+ drm_err(&dev_priv->drm,
	2255	+ "The master control interrupt lied (DE MISC)!\n");
2756	2256	}
2757		- else
2758		- DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2759	2257	}
2760	2258
2761	2259	if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
..	..	@@ -2765,7 +2263,8 @@
2765	2263	ret = IRQ_HANDLED;
2766	2264	gen11_hpd_irq_handler(dev_priv, iir);
2767	2265	} else {
2768		- DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
	2266	+ drm_err(&dev_priv->drm,
	2267	+ "The master control interrupt lied, (DE HPD)!\n");
2769	2268	}
2770	2269	}
2771	2270
..	..	@@ -2778,20 +2277,7 @@
2778	2277	I915_WRITE(GEN8_DE_PORT_IIR, iir);
2779	2278	ret = IRQ_HANDLED;
2780	2279
2781		- tmp_mask = GEN8_AUX_CHANNEL_A;
2782		- if (INTEL_GEN(dev_priv) >= 9)
2783		- tmp_mask \|= GEN9_AUX_CHANNEL_B \|
2784		- GEN9_AUX_CHANNEL_C \|
2785		- GEN9_AUX_CHANNEL_D;
2786		-
2787		- if (INTEL_GEN(dev_priv) >= 11)
2788		- tmp_mask \|= ICL_AUX_CHANNEL_E;
2789		-
2790		- if (IS_CNL_WITH_PORT_F(dev_priv) \|\|
2791		- INTEL_GEN(dev_priv) >= 11)
2792		- tmp_mask \|= CNL_AUX_CHANNEL_F;
2793		-
2794		- if (iir & tmp_mask) {
	2280	+ if (iir & gen8_de_port_aux_mask(dev_priv)) {
2795	2281	dp_aux_irq_handler(dev_priv);
2796	2282	found = true;
2797	2283	}
..	..	@@ -2799,15 +2285,13 @@
2799	2285	if (IS_GEN9_LP(dev_priv)) {
2800	2286	tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2801	2287	if (tmp_mask) {
2802		- bxt_hpd_irq_handler(dev_priv, tmp_mask,
2803		- hpd_bxt);
	2288	+ bxt_hpd_irq_handler(dev_priv, tmp_mask);
2804	2289	found = true;
2805	2290	}
2806	2291	} else if (IS_BROADWELL(dev_priv)) {
2807	2292	tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2808	2293	if (tmp_mask) {
2809		- ilk_hpd_irq_handler(dev_priv,
2810		- tmp_mask, hpd_bdw);
	2294	+ ilk_hpd_irq_handler(dev_priv, tmp_mask);
2811	2295	found = true;
2812	2296	}
2813	2297	}
..	..	@@ -2818,10 +2302,12 @@
2818	2302	}
2819	2303
2820	2304	if (!found)
2821		- DRM_ERROR("Unexpected DE Port interrupt\n");
	2305	+ drm_err(&dev_priv->drm,
	2306	+ "Unexpected DE Port interrupt\n");
2822	2307	}
2823	2308	else
2824		- DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
	2309	+ drm_err(&dev_priv->drm,
	2310	+ "The master control interrupt lied (DE PORT)!\n");
2825	2311	}
2826	2312
2827	2313	for_each_pipe(dev_priv, pipe) {
..	..	@@ -2832,7 +2318,8 @@
2832	2318
2833	2319	iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2834	2320	if (!iir) {
2835		- DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	2321	+ drm_err(&dev_priv->drm,
	2322	+ "The master control interrupt lied (DE PIPE)!\n");
2836	2323	continue;
2837	2324	}
2838	2325
..	..	@@ -2840,7 +2327,7 @@
2840	2327	I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2841	2328
2842	2329	if (iir & GEN8_PIPE_VBLANK)
2843		- drm_handle_vblank(&dev_priv->drm, pipe);
	2330	+ intel_handle_vblank(dev_priv, pipe);
2844	2331
2845	2332	if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2846	2333	hsw_pipe_crc_irq_handler(dev_priv, pipe);
..	..	@@ -2848,16 +2335,12 @@
2848	2335	if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2849	2336	intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2850	2337
2851		- fault_errors = iir;
2852		- if (INTEL_GEN(dev_priv) >= 9)
2853		- fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2854		- else
2855		- fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2856		-
	2338	+ fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2857	2339	if (fault_errors)
2858		- DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2859		- pipe_name(pipe),
2860		- fault_errors);
	2340	+ drm_err(&dev_priv->drm,
	2341	+ "Fault errors on pipe %c: 0x%08x\n",
	2342	+ pipe_name(pipe),
	2343	+ fault_errors);
2861	2344	}
2862	2345
2863	2346	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
..	..	@@ -2872,11 +2355,9 @@
2872	2355	I915_WRITE(SDEIIR, iir);
2873	2356	ret = IRQ_HANDLED;
2874	2357
2875		- if (HAS_PCH_ICP(dev_priv))
	2358	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2876	2359	icp_irq_handler(dev_priv, iir);
2877		- else if (HAS_PCH_SPT(dev_priv) \|\|
2878		- HAS_PCH_KBP(dev_priv) \|\|
2879		- HAS_PCH_CNP(dev_priv))
	2360	+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2880	2361	spt_irq_handler(dev_priv, iir);
2881	2362	else
2882	2363	cpt_irq_handler(dev_priv, iir);
..	..	@@ -2885,218 +2366,66 @@
2885	2366	* Like on previous PCH there seems to be something
2886	2367	* fishy going on with forwarding PCH interrupts.
2887	2368	*/
2888		- DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
	2369	+ drm_dbg(&dev_priv->drm,
	2370	+ "The master control interrupt lied (SDE)!\n");
2889	2371	}
2890	2372	}
2891	2373
2892	2374	return ret;
2893	2375	}
2894	2376
	2377	+static inline u32 gen8_master_intr_disable(void __iomem * const regs)
	2378	+{
	2379	+ raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
	2380	+
	2381	+ /*
	2382	+ * Now with master disabled, get a sample of level indications
	2383	+ * for this interrupt. Indications will be cleared on related acks.
	2384	+ * New indications can and will light up during processing,
	2385	+ * and will generate new interrupt after enabling master.
	2386	+ */
	2387	+ return raw_reg_read(regs, GEN8_MASTER_IRQ);
	2388	+}
	2389	+
	2390	+static inline void gen8_master_intr_enable(void __iomem * const regs)
	2391	+{
	2392	+ raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	2393	+}
	2394	+
2895	2395	static irqreturn_t gen8_irq_handler(int irq, void *arg)
2896	2396	{
2897		- struct drm_i915_private *dev_priv = to_i915(arg);
	2397	+ struct drm_i915_private *dev_priv = arg;
	2398	+ void __iomem * const regs = dev_priv->uncore.regs;
2898	2399	u32 master_ctl;
2899		- u32 gt_iir[4];
2900	2400
2901	2401	if (!intel_irqs_enabled(dev_priv))
2902	2402	return IRQ_NONE;
2903	2403
2904		- master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2905		- master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2906		- if (!master_ctl)
	2404	+ master_ctl = gen8_master_intr_disable(regs);
	2405	+ if (!master_ctl) {
	2406	+ gen8_master_intr_enable(regs);
2907	2407	return IRQ_NONE;
	2408	+ }
2908	2409
2909		- I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2910		-
2911		- /* Find, clear, then process each source of interrupt */
2912		- gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
	2410	+ /* Find, queue (onto bottom-halves), then clear each source */
	2411	+ gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2913	2412
2914	2413	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
2915	2414	if (master_ctl & ~GEN8_GT_IRQS) {
2916		- disable_rpm_wakeref_asserts(dev_priv);
	2415	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2917	2416	gen8_de_irq_handler(dev_priv, master_ctl);
2918		- enable_rpm_wakeref_asserts(dev_priv);
	2417	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2919	2418	}
2920	2419
2921		- I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2922		-
2923		- gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
	2420	+ gen8_master_intr_enable(regs);
2924	2421
2925	2422	return IRQ_HANDLED;
2926	2423	}
2927	2424
2928		-struct wedge_me {
2929		- struct delayed_work work;
2930		- struct drm_i915_private *i915;
2931		- const char *name;
2932		-};
2933		-
2934		-static void wedge_me(struct work_struct *work)
2935		-{
2936		- struct wedge_me w = container_of(work, typeof(w), work.work);
2937		-
2938		- dev_err(w->i915->drm.dev,
2939		- "%s timed out, cancelling all in-flight rendering.\n",
2940		- w->name);
2941		- i915_gem_set_wedged(w->i915);
2942		-}
2943		-
2944		-static void __init_wedge(struct wedge_me *w,
2945		- struct drm_i915_private *i915,
2946		- long timeout,
2947		- const char *name)
2948		-{
2949		- w->i915 = i915;
2950		- w->name = name;
2951		-
2952		- INIT_DELAYED_WORK_ONSTACK(&w->work, wedge_me);
2953		- schedule_delayed_work(&w->work, timeout);
2954		-}
2955		-
2956		-static void __fini_wedge(struct wedge_me *w)
2957		-{
2958		- cancel_delayed_work_sync(&w->work);
2959		- destroy_delayed_work_on_stack(&w->work);
2960		- w->i915 = NULL;
2961		-}
2962		-
2963		-#define i915_wedge_on_timeout(W, DEV, TIMEOUT) \
2964		- for (__init_wedge((W), (DEV), (TIMEOUT), __func__); \
2965		- (W)->i915; \
2966		- __fini_wedge((W)))
2967		-
2968	2425	static u32
2969		-gen11_gt_engine_identity(struct drm_i915_private * const i915,
2970		- const unsigned int bank, const unsigned int bit)
	2426	+gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2971	2427	{
2972		- void __iomem * const regs = i915->regs;
2973		- u32 timeout_ts;
2974		- u32 ident;
2975		-
2976		- lockdep_assert_held(&i915->irq_lock);
2977		-
2978		- raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
2979		-
2980		- /*
2981		- * NB: Specs do not specify how long to spin wait,
2982		- * so we do ~100us as an educated guess.
2983		- */
2984		- timeout_ts = (local_clock() >> 10) + 100;
2985		- do {
2986		- ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
2987		- } while (!(ident & GEN11_INTR_DATA_VALID) &&
2988		- !time_after32(local_clock() >> 10, timeout_ts));
2989		-
2990		- if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
2991		- DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
2992		- bank, bit, ident);
2993		- return 0;
2994		- }
2995		-
2996		- raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
2997		- GEN11_INTR_DATA_VALID);
2998		-
2999		- return ident;
3000		-}
3001		-
3002		-static void
3003		-gen11_other_irq_handler(struct drm_i915_private * const i915,
3004		- const u8 instance, const u16 iir)
3005		-{
3006		- if (instance == OTHER_GTPM_INSTANCE)
3007		- return gen6_rps_irq_handler(i915, iir);
3008		-
3009		- WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
3010		- instance, iir);
3011		-}
3012		-
3013		-static void
3014		-gen11_engine_irq_handler(struct drm_i915_private * const i915,
3015		- const u8 class, const u8 instance, const u16 iir)
3016		-{
3017		- struct intel_engine_cs *engine;
3018		-
3019		- if (instance <= MAX_ENGINE_INSTANCE)
3020		- engine = i915->engine_class[class][instance];
3021		- else
3022		- engine = NULL;
3023		-
3024		- if (likely(engine))
3025		- return gen8_cs_irq_handler(engine, iir);
3026		-
3027		- WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
3028		- class, instance);
3029		-}
3030		-
3031		-static void
3032		-gen11_gt_identity_handler(struct drm_i915_private * const i915,
3033		- const u32 identity)
3034		-{
3035		- const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
3036		- const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
3037		- const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
3038		-
3039		- if (unlikely(!intr))
3040		- return;
3041		-
3042		- if (class <= COPY_ENGINE_CLASS)
3043		- return gen11_engine_irq_handler(i915, class, instance, intr);
3044		-
3045		- if (class == OTHER_CLASS)
3046		- return gen11_other_irq_handler(i915, instance, intr);
3047		-
3048		- WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
3049		- class, instance, intr);
3050		-}
3051		-
3052		-static void
3053		-gen11_gt_bank_handler(struct drm_i915_private * const i915,
3054		- const unsigned int bank)
3055		-{
3056		- void __iomem * const regs = i915->regs;
3057		- unsigned long intr_dw;
3058		- unsigned int bit;
3059		-
3060		- lockdep_assert_held(&i915->irq_lock);
3061		-
3062		- intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
3063		-
3064		- if (unlikely(!intr_dw)) {
3065		- DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
3066		- return;
3067		- }
3068		-
3069		- for_each_set_bit(bit, &intr_dw, 32) {
3070		- const u32 ident = gen11_gt_engine_identity(i915,
3071		- bank, bit);
3072		-
3073		- gen11_gt_identity_handler(i915, ident);
3074		- }
3075		-
3076		- /* Clear must be after shared has been served for engine */
3077		- raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
3078		-}
3079		-
3080		-static void
3081		-gen11_gt_irq_handler(struct drm_i915_private * const i915,
3082		- const u32 master_ctl)
3083		-{
3084		- unsigned int bank;
3085		-
3086		- spin_lock(&i915->irq_lock);
3087		-
3088		- for (bank = 0; bank < 2; bank++) {
3089		- if (master_ctl & GEN11_GT_DW_IRQ(bank))
3090		- gen11_gt_bank_handler(i915, bank);
3091		- }
3092		-
3093		- spin_unlock(&i915->irq_lock);
3094		-}
3095		-
3096		-static u32
3097		-gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
3098		-{
3099		- void __iomem * const regs = dev_priv->regs;
	2428	+ void __iomem * const regs = gt->uncore->regs;
3100	2429	u32 iir;
3101	2430
3102	2431	if (!(master_ctl & GEN11_GU_MISC_IRQ))
..	..	@@ -3110,242 +2439,138 @@
3110	2439	}
3111	2440
3112	2441	static void
3113		-gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)
	2442	+gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
3114	2443	{
3115	2444	if (iir & GEN11_GU_MISC_GSE)
3116		- intel_opregion_asle_intr(dev_priv);
	2445	+ intel_opregion_asle_intr(gt->i915);
3117	2446	}
3118	2447
3119		-static irqreturn_t gen11_irq_handler(int irq, void *arg)
	2448	+static inline u32 gen11_master_intr_disable(void __iomem * const regs)
3120	2449	{
3121		- struct drm_i915_private * const i915 = to_i915(arg);
3122		- void __iomem * const regs = i915->regs;
	2450	+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
	2451	+
	2452	+ /*
	2453	+ * Now with master disabled, get a sample of level indications
	2454	+ * for this interrupt. Indications will be cleared on related acks.
	2455	+ * New indications can and will light up during processing,
	2456	+ * and will generate new interrupt after enabling master.
	2457	+ */
	2458	+ return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
	2459	+}
	2460	+
	2461	+static inline void gen11_master_intr_enable(void __iomem * const regs)
	2462	+{
	2463	+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
	2464	+}
	2465	+
	2466	+static void
	2467	+gen11_display_irq_handler(struct drm_i915_private *i915)
	2468	+{
	2469	+ void __iomem * const regs = i915->uncore.regs;
	2470	+ const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
	2471	+
	2472	+ disable_rpm_wakeref_asserts(&i915->runtime_pm);
	2473	+ /*
	2474	+ * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
	2475	+ * for the display related bits.
	2476	+ */
	2477	+ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
	2478	+ gen8_de_irq_handler(i915, disp_ctl);
	2479	+ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
	2480	+ GEN11_DISPLAY_IRQ_ENABLE);
	2481	+
	2482	+ enable_rpm_wakeref_asserts(&i915->runtime_pm);
	2483	+}
	2484	+
	2485	+static __always_inline irqreturn_t
	2486	+__gen11_irq_handler(struct drm_i915_private * const i915,
	2487	+ u32 (intr_disable)(void __iomem const regs),
	2488	+ void (intr_enable)(void __iomem const regs))
	2489	+{
	2490	+ void __iomem * const regs = i915->uncore.regs;
	2491	+ struct intel_gt *gt = &i915->gt;
3123	2492	u32 master_ctl;
3124	2493	u32 gu_misc_iir;
3125	2494
3126	2495	if (!intel_irqs_enabled(i915))
3127	2496	return IRQ_NONE;
3128	2497
3129		- master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
3130		- master_ctl &= ~GEN11_MASTER_IRQ;
3131		- if (!master_ctl)
	2498	+ master_ctl = intr_disable(regs);
	2499	+ if (!master_ctl) {
	2500	+ intr_enable(regs);
3132	2501	return IRQ_NONE;
3133		-
3134		- /* Disable interrupts. */
3135		- raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
3136		-
3137		- /* Find, clear, then process each source of interrupt. */
3138		- gen11_gt_irq_handler(i915, master_ctl);
3139		-
3140		- /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3141		- if (master_ctl & GEN11_DISPLAY_IRQ) {
3142		- const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
3143		-
3144		- disable_rpm_wakeref_asserts(i915);
3145		- /*
3146		- * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
3147		- * for the display related bits.
3148		- */
3149		- gen8_de_irq_handler(i915, disp_ctl);
3150		- enable_rpm_wakeref_asserts(i915);
3151	2502	}
3152	2503
3153		- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
	2504	+ /* Find, queue (onto bottom-halves), then clear each source */
	2505	+ gen11_gt_irq_handler(gt, master_ctl);
3154	2506
3155		- /* Acknowledge and enable interrupts. */
3156		- raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ \| master_ctl);
	2507	+ /* IRQs are synced during runtime_suspend, we don't require a wakeref */
	2508	+ if (master_ctl & GEN11_DISPLAY_IRQ)
	2509	+ gen11_display_irq_handler(i915);
3157	2510
3158		- gen11_gu_misc_irq_handler(i915, gu_misc_iir);
	2511	+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
	2512	+
	2513	+ intr_enable(regs);
	2514	+
	2515	+ gen11_gu_misc_irq_handler(gt, gu_misc_iir);
3159	2516
3160	2517	return IRQ_HANDLED;
3161	2518	}
3162	2519
3163		-static void i915_reset_device(struct drm_i915_private *dev_priv,
3164		- u32 engine_mask,
3165		- const char *reason)
	2520	+static irqreturn_t gen11_irq_handler(int irq, void *arg)
3166	2521	{
3167		- struct i915_gpu_error *error = &dev_priv->gpu_error;
3168		- struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
3169		- char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
3170		- char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
3171		- char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
3172		- struct wedge_me w;
3173		-
3174		- kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
3175		-
3176		- DRM_DEBUG_DRIVER("resetting chip\n");
3177		- kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
3178		-
3179		- /* Use a watchdog to ensure that our reset completes */
3180		- i915_wedge_on_timeout(&w, dev_priv, 5*HZ) {
3181		- intel_prepare_reset(dev_priv);
3182		-
3183		- error->reason = reason;
3184		- error->stalled_mask = engine_mask;
3185		-
3186		- /* Signal that locked waiters should reset the GPU */
3187		- smp_mb__before_atomic();
3188		- set_bit(I915_RESET_HANDOFF, &error->flags);
3189		- wake_up_all(&error->wait_queue);
3190		-
3191		- /* Wait for anyone holding the lock to wakeup, without
3192		- * blocking indefinitely on struct_mutex.
3193		- */
3194		- do {
3195		- if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
3196		- i915_reset(dev_priv, engine_mask, reason);
3197		- mutex_unlock(&dev_priv->drm.struct_mutex);
3198		- }
3199		- } while (wait_on_bit_timeout(&error->flags,
3200		- I915_RESET_HANDOFF,
3201		- TASK_UNINTERRUPTIBLE,
3202		- 1));
3203		-
3204		- error->stalled_mask = 0;
3205		- error->reason = NULL;
3206		-
3207		- intel_finish_reset(dev_priv);
3208		- }
3209		-
3210		- if (!test_bit(I915_WEDGED, &error->flags))
3211		- kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
	2522	+ return __gen11_irq_handler(arg,
	2523	+ gen11_master_intr_disable,
	2524	+ gen11_master_intr_enable);
3212	2525	}
3213	2526
3214		-static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
	2527	+static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
3215	2528	{
3216		- u32 eir;
	2529	+ u32 val;
3217	2530
3218		- if (!IS_GEN2(dev_priv))
3219		- I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
	2531	+ /* First disable interrupts */
	2532	+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
3220	2533
3221		- if (INTEL_GEN(dev_priv) < 4)
3222		- I915_WRITE(IPEIR, I915_READ(IPEIR));
3223		- else
3224		- I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
	2534	+ /* Get the indication levels and ack the master unit */
	2535	+ val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
	2536	+ if (unlikely(!val))
	2537	+ return 0;
3225	2538
3226		- I915_WRITE(EIR, I915_READ(EIR));
3227		- eir = I915_READ(EIR);
3228		- if (eir) {
3229		- /*
3230		- * some errors might have become stuck,
3231		- * mask them.
3232		- */
3233		- DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
3234		- I915_WRITE(EMR, I915_READ(EMR) \| eir);
3235		- I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT);
3236		- }
	2539	+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
	2540	+
	2541	+ /*
	2542	+ * Now with master disabled, get a sample of level indications
	2543	+ * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
	2544	+ * out as this bit doesn't exist anymore for DG1
	2545	+ */
	2546	+ val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
	2547	+ if (unlikely(!val))
	2548	+ return 0;
	2549	+
	2550	+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
	2551	+
	2552	+ return val;
3237	2553	}
3238	2554
3239		-/**
3240		- * i915_handle_error - handle a gpu error
3241		- * @dev_priv: i915 device private
3242		- * @engine_mask: mask representing engines that are hung
3243		- * @flags: control flags
3244		- * @fmt: Error message format string
3245		- *
3246		- * Do some basic checking of register state at error time and
3247		- * dump it to the syslog. Also call i915_capture_error_state() to make
3248		- * sure we get a record and make it available in debugfs. Fire a uevent
3249		- * so userspace knows something bad happened (should trigger collection
3250		- * of a ring dump etc.).
3251		- */
3252		-void i915_handle_error(struct drm_i915_private *dev_priv,
3253		- u32 engine_mask,
3254		- unsigned long flags,
3255		- const char *fmt, ...)
	2555	+static inline void dg1_master_intr_enable(void __iomem * const regs)
3256	2556	{
3257		- struct intel_engine_cs *engine;
3258		- unsigned int tmp;
3259		- char error_msg[80];
3260		- char *msg = NULL;
	2557	+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
	2558	+}
3261	2559
3262		- if (fmt) {
3263		- va_list args;
3264		-
3265		- va_start(args, fmt);
3266		- vscnprintf(error_msg, sizeof(error_msg), fmt, args);
3267		- va_end(args);
3268		-
3269		- msg = error_msg;
3270		- }
3271		-
3272		- /*
3273		- * In most cases it's guaranteed that we get here with an RPM
3274		- * reference held, for example because there is a pending GPU
3275		- * request that won't finish until the reset is done. This
3276		- * isn't the case at least when we get here by doing a
3277		- * simulated reset via debugfs, so get an RPM reference.
3278		- */
3279		- intel_runtime_pm_get(dev_priv);
3280		-
3281		- engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
3282		-
3283		- if (flags & I915_ERROR_CAPTURE) {
3284		- i915_capture_error_state(dev_priv, engine_mask, msg);
3285		- i915_clear_error_registers(dev_priv);
3286		- }
3287		-
3288		- /*
3289		- * Try engine reset when available. We fall back to full reset if
3290		- * single reset fails.
3291		- */
3292		- if (intel_has_reset_engine(dev_priv)) {
3293		- for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
3294		- BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
3295		- if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3296		- &dev_priv->gpu_error.flags))
3297		- continue;
3298		-
3299		- if (i915_reset_engine(engine, msg) == 0)
3300		- engine_mask &= ~intel_engine_flag(engine);
3301		-
3302		- clear_bit(I915_RESET_ENGINE + engine->id,
3303		- &dev_priv->gpu_error.flags);
3304		- wake_up_bit(&dev_priv->gpu_error.flags,
3305		- I915_RESET_ENGINE + engine->id);
3306		- }
3307		- }
3308		-
3309		- if (!engine_mask)
3310		- goto out;
3311		-
3312		- /* Full reset needs the mutex, stop any other user trying to do so. */
3313		- if (test_and_set_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags)) {
3314		- wait_event(dev_priv->gpu_error.reset_queue,
3315		- !test_bit(I915_RESET_BACKOFF,
3316		- &dev_priv->gpu_error.flags));
3317		- goto out;
3318		- }
3319		-
3320		- /* Prevent any other reset-engine attempt. */
3321		- for_each_engine(engine, dev_priv, tmp) {
3322		- while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
3323		- &dev_priv->gpu_error.flags))
3324		- wait_on_bit(&dev_priv->gpu_error.flags,
3325		- I915_RESET_ENGINE + engine->id,
3326		- TASK_UNINTERRUPTIBLE);
3327		- }
3328		-
3329		- i915_reset_device(dev_priv, engine_mask, msg);
3330		-
3331		- for_each_engine(engine, dev_priv, tmp) {
3332		- clear_bit(I915_RESET_ENGINE + engine->id,
3333		- &dev_priv->gpu_error.flags);
3334		- }
3335		-
3336		- clear_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags);
3337		- wake_up_all(&dev_priv->gpu_error.reset_queue);
3338		-
3339		-out:
3340		- intel_runtime_pm_put(dev_priv);
	2560	+static irqreturn_t dg1_irq_handler(int irq, void *arg)
	2561	+{
	2562	+ return __gen11_irq_handler(arg,
	2563	+ dg1_master_intr_disable_and_ack,
	2564	+ dg1_master_intr_enable);
3341	2565	}
3342	2566
3343	2567	/* Called from drm generic code, passed 'crtc' which
3344	2568	* we use as a pipe index
3345	2569	*/
3346		-static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2570	+int i8xx_enable_vblank(struct drm_crtc *crtc)
3347	2571	{
3348		- struct drm_i915_private *dev_priv = to_i915(dev);
	2572	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2573	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3349	2574	unsigned long irqflags;
3350	2575
3351	2576	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3355,9 +2580,26 @@
3355	2580	return 0;
3356	2581	}
3357	2582
3358		-static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2583	+int i915gm_enable_vblank(struct drm_crtc *crtc)
3359	2584	{
3360		- struct drm_i915_private *dev_priv = to_i915(dev);
	2585	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2586	+
	2587	+ /*
	2588	+ * Vblank interrupts fail to wake the device up from C2+.
	2589	+ * Disabling render clock gating during C-states avoids
	2590	+ * the problem. There is a small power cost so we do this
	2591	+ * only when vblank interrupts are actually enabled.
	2592	+ */
	2593	+ if (dev_priv->vblank_enabled++ == 0)
	2594	+ I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
	2595	+
	2596	+ return i8xx_enable_vblank(crtc);
	2597	+}
	2598	+
	2599	+int i965_enable_vblank(struct drm_crtc *crtc)
	2600	+{
	2601	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2602	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3361	2603	unsigned long irqflags;
3362	2604
3363	2605	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3368,11 +2610,12 @@
3368	2610	return 0;
3369	2611	}
3370	2612
3371		-static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2613	+int ilk_enable_vblank(struct drm_crtc *crtc)
3372	2614	{
3373		- struct drm_i915_private *dev_priv = to_i915(dev);
	2615	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2616	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3374	2617	unsigned long irqflags;
3375		- uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
	2618	+ u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3376	2619	DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3377	2620
3378	2621	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3383,14 +2626,15 @@
3383	2626	* PSR is active as no frames are generated.
3384	2627	*/
3385	2628	if (HAS_PSR(dev_priv))
3386		- drm_vblank_restore(dev, pipe);
	2629	+ drm_crtc_vblank_restore(crtc);
3387	2630
3388	2631	return 0;
3389	2632	}
3390	2633
3391		-static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
	2634	+int bdw_enable_vblank(struct drm_crtc *crtc)
3392	2635	{
3393		- struct drm_i915_private *dev_priv = to_i915(dev);
	2636	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2637	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3394	2638	unsigned long irqflags;
3395	2639
3396	2640	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3401,7 +2645,7 @@
3401	2645	* PSR is active as no frames are generated, so check only for PSR.
3402	2646	*/
3403	2647	if (HAS_PSR(dev_priv))
3404		- drm_vblank_restore(dev, pipe);
	2648	+ drm_crtc_vblank_restore(crtc);
3405	2649
3406	2650	return 0;
3407	2651	}
..	..	@@ -3409,9 +2653,10 @@
3409	2653	/* Called from drm generic code, passed 'crtc' which
3410	2654	* we use as a pipe index
3411	2655	*/
3412		-static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2656	+void i8xx_disable_vblank(struct drm_crtc *crtc)
3413	2657	{
3414		- struct drm_i915_private *dev_priv = to_i915(dev);
	2658	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2659	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3415	2660	unsigned long irqflags;
3416	2661
3417	2662	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3419,9 +2664,20 @@
3419	2664	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3420	2665	}
3421	2666
3422		-static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2667	+void i915gm_disable_vblank(struct drm_crtc *crtc)
3423	2668	{
3424		- struct drm_i915_private *dev_priv = to_i915(dev);
	2669	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2670	+
	2671	+ i8xx_disable_vblank(crtc);
	2672	+
	2673	+ if (--dev_priv->vblank_enabled == 0)
	2674	+ I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
	2675	+}
	2676	+
	2677	+void i965_disable_vblank(struct drm_crtc *crtc)
	2678	+{
	2679	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2680	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3425	2681	unsigned long irqflags;
3426	2682
3427	2683	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3430,11 +2686,12 @@
3430	2686	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3431	2687	}
3432	2688
3433		-static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2689	+void ilk_disable_vblank(struct drm_crtc *crtc)
3434	2690	{
3435		- struct drm_i915_private *dev_priv = to_i915(dev);
	2691	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2692	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3436	2693	unsigned long irqflags;
3437		- uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
	2694	+ u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3438	2695	DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3439	2696
3440	2697	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3442,9 +2699,10 @@
3442	2699	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3443	2700	}
3444	2701
3445		-static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
	2702	+void bdw_disable_vblank(struct drm_crtc *crtc)
3446	2703	{
3447		- struct drm_i915_private *dev_priv = to_i915(dev);
	2704	+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
	2705	+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
3448	2706	unsigned long irqflags;
3449	2707
3450	2708	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
..	..	@@ -3454,10 +2712,12 @@
3454	2712
3455	2713	static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3456	2714	{
	2715	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2716	+
3457	2717	if (HAS_PCH_NOP(dev_priv))
3458	2718	return;
3459	2719
3460		- GEN3_IRQ_RESET(SDE);
	2720	+ GEN3_IRQ_RESET(uncore, SDE);
3461	2721
3462	2722	if (HAS_PCH_CPT(dev_priv) \|\| HAS_PCH_LPT(dev_priv))
3463	2723	I915_WRITE(SERR_INT, 0xffffffff);
..	..	@@ -3471,43 +2731,38 @@
3471	2731	*
3472	2732	* This function needs to be called before interrupts are enabled.
3473	2733	*/
3474		-static void ibx_irq_pre_postinstall(struct drm_device *dev)
	2734	+static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
3475	2735	{
3476		- struct drm_i915_private *dev_priv = to_i915(dev);
3477		-
3478	2736	if (HAS_PCH_NOP(dev_priv))
3479	2737	return;
3480	2738
3481		- WARN_ON(I915_READ(SDEIER) != 0);
	2739	+ drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3482	2740	I915_WRITE(SDEIER, 0xffffffff);
3483	2741	POSTING_READ(SDEIER);
3484	2742	}
3485	2743
3486		-static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
3487		-{
3488		- GEN3_IRQ_RESET(GT);
3489		- if (INTEL_GEN(dev_priv) >= 6)
3490		- GEN3_IRQ_RESET(GEN6_PM);
3491		-}
3492		-
3493	2744	static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3494	2745	{
	2746	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2747	+
3495	2748	if (IS_CHERRYVIEW(dev_priv))
3496		- I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
	2749	+ intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3497	2750	else
3498		- I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	2751	+ intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
3499	2752
3500	2753	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3501		- I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	2754	+ intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3502	2755
3503	2756	i9xx_pipestat_irq_reset(dev_priv);
3504	2757
3505		- GEN3_IRQ_RESET(VLV_);
	2758	+ GEN3_IRQ_RESET(uncore, VLV_);
3506	2759	dev_priv->irq_mask = ~0u;
3507	2760	}
3508	2761
3509	2762	static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3510	2763	{
	2764	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2765	+
3511	2766	u32 pipestat_mask;
3512	2767	u32 enable_mask;
3513	2768	enum pipe pipe;
..	..	@@ -3528,44 +2783,39 @@
3528	2783	enable_mask \|= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT \|
3529	2784	I915_LPE_PIPE_C_INTERRUPT;
3530	2785
3531		- WARN_ON(dev_priv->irq_mask != ~0u);
	2786	+ drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
3532	2787
3533	2788	dev_priv->irq_mask = ~enable_mask;
3534	2789
3535		- GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
	2790	+ GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3536	2791	}
3537	2792
3538	2793	/* drm_dma.h hooks
3539	2794	*/
3540		-static void ironlake_irq_reset(struct drm_device *dev)
	2795	+static void ilk_irq_reset(struct drm_i915_private *dev_priv)
3541	2796	{
3542		- struct drm_i915_private *dev_priv = to_i915(dev);
	2797	+ struct intel_uncore *uncore = &dev_priv->uncore;
3543	2798
3544		- if (IS_GEN5(dev_priv))
3545		- I915_WRITE(HWSTAM, 0xffffffff);
3546		-
3547		- GEN3_IRQ_RESET(DE);
3548		- if (IS_GEN7(dev_priv))
3549		- I915_WRITE(GEN7_ERR_INT, 0xffffffff);
	2799	+ GEN3_IRQ_RESET(uncore, DE);
	2800	+ if (IS_GEN(dev_priv, 7))
	2801	+ intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3550	2802
3551	2803	if (IS_HASWELL(dev_priv)) {
3552		- I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3553		- I915_WRITE(EDP_PSR_IIR, 0xffffffff);
	2804	+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
	2805	+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3554	2806	}
3555	2807
3556		- gen5_gt_irq_reset(dev_priv);
	2808	+ gen5_gt_irq_reset(&dev_priv->gt);
3557	2809
3558	2810	ibx_irq_reset(dev_priv);
3559	2811	}
3560	2812
3561		-static void valleyview_irq_reset(struct drm_device *dev)
	2813	+static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3562	2814	{
3563		- struct drm_i915_private *dev_priv = to_i915(dev);
3564		-
3565	2815	I915_WRITE(VLV_MASTER_IER, 0);
3566	2816	POSTING_READ(VLV_MASTER_IER);
3567	2817
3568		- gen5_gt_irq_reset(dev_priv);
	2818	+ gen5_gt_irq_reset(&dev_priv->gt);
3569	2819
3570	2820	spin_lock_irq(&dev_priv->irq_lock);
3571	2821	if (dev_priv->display_irqs_enabled)
..	..	@@ -3573,88 +2823,101 @@
3573	2823	spin_unlock_irq(&dev_priv->irq_lock);
3574	2824	}
3575	2825
3576		-static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
	2826	+static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3577	2827	{
3578		- GEN8_IRQ_RESET_NDX(GT, 0);
3579		- GEN8_IRQ_RESET_NDX(GT, 1);
3580		- GEN8_IRQ_RESET_NDX(GT, 2);
3581		- GEN8_IRQ_RESET_NDX(GT, 3);
3582		-}
	2828	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2829	+ enum pipe pipe;
3583	2830
3584		-static void gen8_irq_reset(struct drm_device *dev)
3585		-{
3586		- struct drm_i915_private *dev_priv = to_i915(dev);
3587		- int pipe;
	2831	+ gen8_master_intr_disable(dev_priv->uncore.regs);
3588	2832
3589		- I915_WRITE(GEN8_MASTER_IRQ, 0);
3590		- POSTING_READ(GEN8_MASTER_IRQ);
	2833	+ gen8_gt_irq_reset(&dev_priv->gt);
3591	2834
3592		- gen8_gt_irq_reset(dev_priv);
3593		-
3594		- I915_WRITE(EDP_PSR_IMR, 0xffffffff);
3595		- I915_WRITE(EDP_PSR_IIR, 0xffffffff);
	2835	+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
	2836	+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3596	2837
3597	2838	for_each_pipe(dev_priv, pipe)
3598	2839	if (intel_display_power_is_enabled(dev_priv,
3599	2840	POWER_DOMAIN_PIPE(pipe)))
3600		- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
	2841	+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3601	2842
3602		- GEN3_IRQ_RESET(GEN8_DE_PORT_);
3603		- GEN3_IRQ_RESET(GEN8_DE_MISC_);
3604		- GEN3_IRQ_RESET(GEN8_PCU_);
	2843	+ GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
	2844	+ GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
	2845	+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3605	2846
3606	2847	if (HAS_PCH_SPLIT(dev_priv))
3607	2848	ibx_irq_reset(dev_priv);
3608	2849	}
3609	2850
3610		-static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
	2851	+static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
3611	2852	{
3612		- /* Disable RCS, BCS, VCS and VECS class engines. */
3613		- I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
3614		- I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
	2853	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2854	+ enum pipe pipe;
	2855	+ u32 trans_mask = BIT(TRANSCODER_A) \| BIT(TRANSCODER_B) \|
	2856	+ BIT(TRANSCODER_C) \| BIT(TRANSCODER_D);
3615	2857
3616		- /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
3617		- I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
3618		- I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
3619		- I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
3620		- I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
3621		- I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
	2858	+ intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3622	2859
3623		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
3624		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
3625		-}
	2860	+ if (INTEL_GEN(dev_priv) >= 12) {
	2861	+ enum transcoder trans;
3626	2862
3627		-static void gen11_irq_reset(struct drm_device *dev)
3628		-{
3629		- struct drm_i915_private *dev_priv = dev->dev_private;
3630		- int pipe;
	2863	+ for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
	2864	+ enum intel_display_power_domain domain;
3631	2865
3632		- I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
3633		- POSTING_READ(GEN11_GFX_MSTR_IRQ);
	2866	+ domain = POWER_DOMAIN_TRANSCODER(trans);
	2867	+ if (!intel_display_power_is_enabled(dev_priv, domain))
	2868	+ continue;
3634	2869
3635		- gen11_gt_irq_reset(dev_priv);
3636		-
3637		- I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
	2870	+ intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
	2871	+ intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
	2872	+ }
	2873	+ } else {
	2874	+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
	2875	+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
	2876	+ }
3638	2877
3639	2878	for_each_pipe(dev_priv, pipe)
3640	2879	if (intel_display_power_is_enabled(dev_priv,
3641	2880	POWER_DOMAIN_PIPE(pipe)))
3642		- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
	2881	+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3643	2882
3644		- GEN3_IRQ_RESET(GEN8_DE_PORT_);
3645		- GEN3_IRQ_RESET(GEN8_DE_MISC_);
3646		- GEN3_IRQ_RESET(GEN11_DE_HPD_);
3647		- GEN3_IRQ_RESET(GEN11_GU_MISC_);
3648		- GEN3_IRQ_RESET(GEN8_PCU_);
	2883	+ GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
	2884	+ GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
	2885	+ GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3649	2886
3650		- if (HAS_PCH_ICP(dev_priv))
3651		- GEN3_IRQ_RESET(SDE);
	2887	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	2888	+ GEN3_IRQ_RESET(uncore, SDE);
	2889	+
	2890	+ /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
	2891	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
	2892	+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
	2893	+ SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
	2894	+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
	2895	+ SBCLK_RUN_REFCLK_DIS, 0);
	2896	+ }
	2897	+}
	2898	+
	2899	+static void gen11_irq_reset(struct drm_i915_private *dev_priv)
	2900	+{
	2901	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2902	+
	2903	+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
	2904	+ dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
	2905	+ else
	2906	+ gen11_master_intr_disable(dev_priv->uncore.regs);
	2907	+
	2908	+ gen11_gt_irq_reset(&dev_priv->gt);
	2909	+ gen11_display_irq_reset(dev_priv);
	2910	+
	2911	+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
	2912	+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3652	2913	}
3653	2914
3654	2915	void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3655	2916	u8 pipe_mask)
3656	2917	{
3657		- uint32_t extra_ier = GEN8_PIPE_VBLANK \| GEN8_PIPE_FIFO_UNDERRUN;
	2918	+ struct intel_uncore *uncore = &dev_priv->uncore;
	2919	+
	2920	+ u32 extra_ier = GEN8_PIPE_VBLANK \| GEN8_PIPE_FIFO_UNDERRUN;
3658	2921	enum pipe pipe;
3659	2922
3660	2923	spin_lock_irq(&dev_priv->irq_lock);
..	..	@@ -3665,7 +2928,7 @@
3665	2928	}
3666	2929
3667	2930	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3668		- GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
	2931	+ GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3669	2932	dev_priv->de_irq_mask[pipe],
3670	2933	~dev_priv->de_irq_mask[pipe] \| extra_ier);
3671	2934
..	..	@@ -3675,6 +2938,7 @@
3675	2938	void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3676	2939	u8 pipe_mask)
3677	2940	{
	2941	+ struct intel_uncore *uncore = &dev_priv->uncore;
3678	2942	enum pipe pipe;
3679	2943
3680	2944	spin_lock_irq(&dev_priv->irq_lock);
..	..	@@ -3685,24 +2949,24 @@
3685	2949	}
3686	2950
3687	2951	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3688		- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
	2952	+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3689	2953
3690	2954	spin_unlock_irq(&dev_priv->irq_lock);
3691	2955
3692	2956	/* make sure we're done processing display irqs */
3693		- synchronize_irq(dev_priv->drm.irq);
	2957	+ intel_synchronize_irq(dev_priv);
3694	2958	}
3695	2959
3696		-static void cherryview_irq_reset(struct drm_device *dev)
	2960	+static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3697	2961	{
3698		- struct drm_i915_private *dev_priv = to_i915(dev);
	2962	+ struct intel_uncore *uncore = &dev_priv->uncore;
3699	2963
3700	2964	I915_WRITE(GEN8_MASTER_IRQ, 0);
3701	2965	POSTING_READ(GEN8_MASTER_IRQ);
3702	2966
3703		- gen8_gt_irq_reset(dev_priv);
	2967	+ gen8_gt_irq_reset(&dev_priv->gt);
3704	2968
3705		- GEN3_IRQ_RESET(GEN8_PCU_);
	2969	+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3706	2970
3707	2971	spin_lock_irq(&dev_priv->irq_lock);
3708	2972	if (dev_priv->display_irqs_enabled)
..	..	@@ -3721,6 +2985,18 @@
3721	2985	enabled_irqs \|= hpd[encoder->hpd_pin];
3722	2986
3723	2987	return enabled_irqs;
	2988	+}
	2989	+
	2990	+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
	2991	+ const u32 hpd[HPD_NUM_PINS])
	2992	+{
	2993	+ struct intel_encoder *encoder;
	2994	+ u32 hotplug_irqs = 0;
	2995	+
	2996	+ for_each_intel_encoder(&dev_priv->drm, encoder)
	2997	+ hotplug_irqs \|= hpd[encoder->hpd_pin];
	2998	+
	2999	+ return hotplug_irqs;
3724	3000	}
3725	3001
3726	3002	static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
..	..	@@ -3752,46 +3028,71 @@
3752	3028	{
3753	3029	u32 hotplug_irqs, enabled_irqs;
3754	3030
3755		- if (HAS_PCH_IBX(dev_priv)) {
3756		- hotplug_irqs = SDE_HOTPLUG_MASK;
3757		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3758		- } else {
3759		- hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3760		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3761		- }
	3031	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3032	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3762	3033
3763	3034	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3764	3035
3765	3036	ibx_hpd_detection_setup(dev_priv);
3766	3037	}
3767	3038
3768		-static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
	3039	+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
	3040	+ u32 enable_mask)
3769	3041	{
3770	3042	u32 hotplug;
3771	3043
3772	3044	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3773		- hotplug \|= ICP_DDIA_HPD_ENABLE \|
3774		- ICP_DDIB_HPD_ENABLE;
	3045	+ hotplug \|= enable_mask;
3775	3046	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
	3047	+}
	3048	+
	3049	+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
	3050	+ u32 enable_mask)
	3051	+{
	3052	+ u32 hotplug;
3776	3053
3777	3054	hotplug = I915_READ(SHOTPLUG_CTL_TC);
3778		- hotplug \|= ICP_TC_HPD_ENABLE(PORT_TC1) \|
3779		- ICP_TC_HPD_ENABLE(PORT_TC2) \|
3780		- ICP_TC_HPD_ENABLE(PORT_TC3) \|
3781		- ICP_TC_HPD_ENABLE(PORT_TC4);
	3055	+ hotplug \|= enable_mask;
3782	3056	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3783	3057	}
3784	3058
3785		-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
	3059	+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
	3060	+ u32 ddi_enable_mask, u32 tc_enable_mask)
3786	3061	{
3787	3062	u32 hotplug_irqs, enabled_irqs;
3788	3063
3789		- hotplug_irqs = SDE_DDI_MASK_ICP \| SDE_TC_MASK_ICP;
3790		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
	3064	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3065	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3066	+
	3067	+ if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
	3068	+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3791	3069
3792	3070	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3793	3071
3794		- icp_hpd_detection_setup(dev_priv);
	3072	+ icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
	3073	+ if (tc_enable_mask)
	3074	+ icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
	3075	+}
	3076	+
	3077	+/*
	3078	+ * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
	3079	+ * equivalent of SDE.
	3080	+ */
	3081	+static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
	3082	+{
	3083	+ icp_hpd_irq_setup(dev_priv,
	3084	+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
	3085	+}
	3086	+
	3087	+/*
	3088	+ * JSP behaves exactly the same as MCC above except that port C is mapped to
	3089	+ * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
	3090	+ * masks & tables rather than ICP's masks & tables.
	3091	+ */
	3092	+static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
	3093	+{
	3094	+ icp_hpd_irq_setup(dev_priv,
	3095	+ TGP_DDI_HPD_ENABLE_MASK, 0);
3795	3096	}
3796	3097
3797	3098	static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
..	..	@@ -3802,14 +3103,18 @@
3802	3103	hotplug \|= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) \|
3803	3104	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) \|
3804	3105	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) \|
3805		- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
	3106	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) \|
	3107	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) \|
	3108	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
3806	3109	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3807	3110
3808	3111	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3809	3112	hotplug \|= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) \|
3810	3113	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) \|
3811	3114	GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) \|
3812		- GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
	3115	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) \|
	3116	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) \|
	3117	+ GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
3813	3118	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3814	3119	}
3815	3120
..	..	@@ -3818,8 +3123,8 @@
3818	3123	u32 hotplug_irqs, enabled_irqs;
3819	3124	u32 val;
3820	3125
3821		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
3822		- hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK \| GEN11_DE_TBT_HOTPLUG_MASK;
	3126	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
	3127	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3823	3128
3824	3129	val = I915_READ(GEN11_DE_HPD_IMR);
3825	3130	val &= ~hotplug_irqs;
..	..	@@ -3829,8 +3134,12 @@
3829	3134
3830	3135	gen11_hpd_detection_setup(dev_priv);
3831	3136
3832		- if (HAS_PCH_ICP(dev_priv))
3833		- icp_hpd_irq_setup(dev_priv);
	3137	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
	3138	+ icp_hpd_irq_setup(dev_priv,
	3139	+ TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
	3140	+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	3141	+ icp_hpd_irq_setup(dev_priv,
	3142	+ ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3834	3143	}
3835	3144
3836	3145	static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
..	..	@@ -3862,8 +3171,11 @@
3862	3171	{
3863	3172	u32 hotplug_irqs, enabled_irqs;
3864	3173
3865		- hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3866		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
	3174	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
	3175	+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
	3176	+
	3177	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
	3178	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3867	3179
3868	3180	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3869	3181
..	..	@@ -3890,22 +3202,13 @@
3890	3202	{
3891	3203	u32 hotplug_irqs, enabled_irqs;
3892	3204
3893		- if (INTEL_GEN(dev_priv) >= 8) {
3894		- hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3895		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
	3205	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
	3206	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3896	3207
	3208	+ if (INTEL_GEN(dev_priv) >= 8)
3897	3209	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3898		- } else if (INTEL_GEN(dev_priv) >= 7) {
3899		- hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3900		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3901		-
	3210	+ else
3902	3211	ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3903		- } else {
3904		- hotplug_irqs = DE_DP_A_HOTPLUG;
3905		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3906		-
3907		- ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3908		- }
3909	3212
3910	3213	ilk_hpd_detection_setup(dev_priv);
3911	3214
..	..	@@ -3922,8 +3225,9 @@
3922	3225	PORTB_HOTPLUG_ENABLE \|
3923	3226	PORTC_HOTPLUG_ENABLE;
3924	3227
3925		- DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3926		- hotplug, enabled_irqs);
	3228	+ drm_dbg_kms(&dev_priv->drm,
	3229	+ "Invert bit setting: hp_ctl:%x hp_port:%x\n",
	3230	+ hotplug, enabled_irqs);
3927	3231	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3928	3232
3929	3233	/*
..	..	@@ -3952,17 +3256,16 @@
3952	3256	{
3953	3257	u32 hotplug_irqs, enabled_irqs;
3954	3258
3955		- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3956		- hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
	3259	+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
	3260	+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
3957	3261
3958	3262	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3959	3263
3960	3264	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3961	3265	}
3962	3266
3963		-static void ibx_irq_postinstall(struct drm_device *dev)
	3267	+static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3964	3268	{
3965		- struct drm_i915_private *dev_priv = to_i915(dev);
3966	3269	u32 mask;
3967	3270
3968	3271	if (HAS_PCH_NOP(dev_priv))
..	..	@@ -3975,7 +3278,7 @@
3975	3278	else
3976	3279	mask = SDE_GMBUS_CPT;
3977	3280
3978		- gen3_assert_iir_is_zero(dev_priv, SDEIIR);
	3281	+ gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3979	3282	I915_WRITE(SDEIMR, ~mask);
3980	3283
3981	3284	if (HAS_PCH_IBX(dev_priv) \|\| HAS_PCH_CPT(dev_priv) \|\|
..	..	@@ -3985,47 +3288,9 @@
3985	3288	spt_hpd_detection_setup(dev_priv);
3986	3289	}
3987	3290
3988		-static void gen5_gt_irq_postinstall(struct drm_device *dev)
	3291	+static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3989	3292	{
3990		- struct drm_i915_private *dev_priv = to_i915(dev);
3991		- u32 pm_irqs, gt_irqs;
3992		-
3993		- pm_irqs = gt_irqs = 0;
3994		-
3995		- dev_priv->gt_irq_mask = ~0;
3996		- if (HAS_L3_DPF(dev_priv)) {
3997		- /* L3 parity interrupt is always unmasked. */
3998		- dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3999		- gt_irqs \|= GT_PARITY_ERROR(dev_priv);
4000		- }
4001		-
4002		- gt_irqs \|= GT_RENDER_USER_INTERRUPT;
4003		- if (IS_GEN5(dev_priv)) {
4004		- gt_irqs \|= ILK_BSD_USER_INTERRUPT;
4005		- } else {
4006		- gt_irqs \|= GT_BLT_USER_INTERRUPT \| GT_BSD_USER_INTERRUPT;
4007		- }
4008		-
4009		- GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
4010		-
4011		- if (INTEL_GEN(dev_priv) >= 6) {
4012		- /*
4013		- * RPS interrupts will get enabled/disabled on demand when RPS
4014		- * itself is enabled/disabled.
4015		- */
4016		- if (HAS_VEBOX(dev_priv)) {
4017		- pm_irqs \|= PM_VEBOX_USER_INTERRUPT;
4018		- dev_priv->pm_ier \|= PM_VEBOX_USER_INTERRUPT;
4019		- }
4020		-
4021		- dev_priv->pm_imr = 0xffffffff;
4022		- GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
4023		- }
4024		-}
4025		-
4026		-static int ironlake_irq_postinstall(struct drm_device *dev)
4027		-{
4028		- struct drm_i915_private *dev_priv = to_i915(dev);
	3293	+ struct intel_uncore *uncore = &dev_priv->uncore;
4029	3294	u32 display_mask, extra_mask;
4030	3295
4031	3296	if (INTEL_GEN(dev_priv) >= 7) {
..	..	@@ -4044,22 +3309,22 @@
4044	3309	}
4045	3310
4046	3311	if (IS_HASWELL(dev_priv)) {
4047		- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
4048		- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
	3312	+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
4049	3313	display_mask \|= DE_EDP_PSR_INT_HSW;
4050	3314	}
4051	3315
4052	3316	dev_priv->irq_mask = ~display_mask;
4053	3317
4054		- ibx_irq_pre_postinstall(dev);
	3318	+ ibx_irq_pre_postinstall(dev_priv);
4055	3319
4056		- GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask \| extra_mask);
	3320	+ GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
	3321	+ display_mask \| extra_mask);
4057	3322
4058		- gen5_gt_irq_postinstall(dev);
	3323	+ gen5_gt_irq_postinstall(&dev_priv->gt);
4059	3324
4060	3325	ilk_hpd_detection_setup(dev_priv);
4061	3326
4062		- ibx_irq_postinstall(dev);
	3327	+ ibx_irq_postinstall(dev_priv);
4063	3328
4064	3329	if (IS_IRONLAKE_M(dev_priv)) {
4065	3330	/* Enable PCU event interrupts
..	..	@@ -4071,8 +3336,6 @@
4071	3336	ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
4072	3337	spin_unlock_irq(&dev_priv->irq_lock);
4073	3338	}
4074		-
4075		- return 0;
4076	3339	}
4077	3340
4078	3341	void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
..	..	@@ -4104,11 +3367,9 @@
4104	3367	}
4105	3368
4106	3369
4107		-static int valleyview_irq_postinstall(struct drm_device *dev)
	3370	+static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
4108	3371	{
4109		- struct drm_i915_private *dev_priv = to_i915(dev);
4110		-
4111		- gen5_gt_irq_postinstall(dev);
	3372	+ gen5_gt_irq_postinstall(&dev_priv->gt);
4112	3373
4113	3374	spin_lock_irq(&dev_priv->irq_lock);
4114	3375	if (dev_priv->display_irqs_enabled)
..	..	@@ -4117,69 +3378,27 @@
4117	3378
4118	3379	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
4119	3380	POSTING_READ(VLV_MASTER_IER);
4120		-
4121		- return 0;
4122		-}
4123		-
4124		-static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
4125		-{
4126		- /* These are interrupts we'll toggle with the ring mask register */
4127		- uint32_t gt_interrupts[] = {
4128		- GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT \|
4129		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT \|
4130		- GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT \|
4131		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
4132		- GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT \|
4133		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT \|
4134		- GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT \|
4135		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
4136		- 0,
4137		- GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT \|
4138		- GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
4139		- };
4140		-
4141		- if (HAS_L3_DPF(dev_priv))
4142		- gt_interrupts[0] \|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
4143		-
4144		- dev_priv->pm_ier = 0x0;
4145		- dev_priv->pm_imr = ~dev_priv->pm_ier;
4146		- GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
4147		- GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
4148		- /*
4149		- * RPS interrupts will get enabled/disabled on demand when RPS itself
4150		- * is enabled/disabled. Same wil be the case for GuC interrupts.
4151		- */
4152		- GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
4153		- GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
4154	3381	}
4155	3382
4156	3383	static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
4157	3384	{
4158		- uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
4159		- uint32_t de_pipe_enables;
4160		- u32 de_port_masked = GEN8_AUX_CHANNEL_A;
	3385	+ struct intel_uncore *uncore = &dev_priv->uncore;
	3386	+
	3387	+ u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) \|
	3388	+ GEN8_PIPE_CDCLK_CRC_DONE;
	3389	+ u32 de_pipe_enables;
	3390	+ u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
4161	3391	u32 de_port_enables;
4162	3392	u32 de_misc_masked = GEN8_DE_EDP_PSR;
	3393	+ u32 trans_mask = BIT(TRANSCODER_A) \| BIT(TRANSCODER_B) \|
	3394	+ BIT(TRANSCODER_C) \| BIT(TRANSCODER_D);
4163	3395	enum pipe pipe;
4164	3396
4165	3397	if (INTEL_GEN(dev_priv) <= 10)
4166	3398	de_misc_masked \|= GEN8_DE_MISC_GSE;
4167	3399
4168		- if (INTEL_GEN(dev_priv) >= 9) {
4169		- de_pipe_masked \|= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
4170		- de_port_masked \|= GEN9_AUX_CHANNEL_B \| GEN9_AUX_CHANNEL_C \|
4171		- GEN9_AUX_CHANNEL_D;
4172		- if (IS_GEN9_LP(dev_priv))
4173		- de_port_masked \|= BXT_DE_PORT_GMBUS;
4174		- } else {
4175		- de_pipe_masked \|= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
4176		- }
4177		-
4178		- if (INTEL_GEN(dev_priv) >= 11)
4179		- de_port_masked \|= ICL_AUX_CHANNEL_E;
4180		-
4181		- if (IS_CNL_WITH_PORT_F(dev_priv) \|\| INTEL_GEN(dev_priv) >= 11)
4182		- de_port_masked \|= CNL_AUX_CHANNEL_F;
	3400	+ if (IS_GEN9_LP(dev_priv))
	3401	+ de_port_masked \|= BXT_DE_PORT_GMBUS;
4183	3402
4184	3403	de_pipe_enables = de_pipe_masked \| GEN8_PIPE_VBLANK \|
4185	3404	GEN8_PIPE_FIFO_UNDERRUN;
..	..	@@ -4190,28 +3409,42 @@
4190	3409	else if (IS_BROADWELL(dev_priv))
4191	3410	de_port_enables \|= GEN8_PORT_DP_A_HOTPLUG;
4192	3411
4193		- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
4194		- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
	3412	+ if (INTEL_GEN(dev_priv) >= 12) {
	3413	+ enum transcoder trans;
	3414	+
	3415	+ for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
	3416	+ enum intel_display_power_domain domain;
	3417	+
	3418	+ domain = POWER_DOMAIN_TRANSCODER(trans);
	3419	+ if (!intel_display_power_is_enabled(dev_priv, domain))
	3420	+ continue;
	3421	+
	3422	+ gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
	3423	+ }
	3424	+ } else {
	3425	+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
	3426	+ }
4195	3427
4196	3428	for_each_pipe(dev_priv, pipe) {
4197	3429	dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
4198	3430
4199	3431	if (intel_display_power_is_enabled(dev_priv,
4200	3432	POWER_DOMAIN_PIPE(pipe)))
4201		- GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
	3433	+ GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
4202	3434	dev_priv->de_irq_mask[pipe],
4203	3435	de_pipe_enables);
4204	3436	}
4205	3437
4206		- GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
4207		- GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
	3438	+ GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
	3439	+ GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
4208	3440
4209	3441	if (INTEL_GEN(dev_priv) >= 11) {
4210	3442	u32 de_hpd_masked = 0;
4211	3443	u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK \|
4212	3444	GEN11_DE_TBT_HOTPLUG_MASK;
4213	3445
4214		- GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
	3446	+ GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
	3447	+ de_hpd_enables);
4215	3448	gen11_hpd_detection_setup(dev_priv);
4216	3449	} else if (IS_GEN9_LP(dev_priv)) {
4217	3450	bxt_hpd_detection_setup(dev_priv);
..	..	@@ -4220,93 +3453,72 @@
4220	3453	}
4221	3454	}
4222	3455
4223		-static int gen8_irq_postinstall(struct drm_device *dev)
	3456	+static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
4224	3457	{
4225		- struct drm_i915_private *dev_priv = to_i915(dev);
4226		-
4227	3458	if (HAS_PCH_SPLIT(dev_priv))
4228		- ibx_irq_pre_postinstall(dev);
	3459	+ ibx_irq_pre_postinstall(dev_priv);
4229	3460
4230		- gen8_gt_irq_postinstall(dev_priv);
	3461	+ gen8_gt_irq_postinstall(&dev_priv->gt);
4231	3462	gen8_de_irq_postinstall(dev_priv);
4232	3463
4233	3464	if (HAS_PCH_SPLIT(dev_priv))
4234		- ibx_irq_postinstall(dev);
	3465	+ ibx_irq_postinstall(dev_priv);
4235	3466
4236		- I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4237		- POSTING_READ(GEN8_MASTER_IRQ);
4238		-
4239		- return 0;
	3467	+ gen8_master_intr_enable(dev_priv->uncore.regs);
4240	3468	}
4241	3469
4242		-static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
	3470	+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
4243	3471	{
4244		- const u32 irqs = GT_RENDER_USER_INTERRUPT \| GT_CONTEXT_SWITCH_INTERRUPT;
4245		-
4246		- BUILD_BUG_ON(irqs & 0xffff0000);
4247		-
4248		- /* Enable RCS, BCS, VCS and VECS class interrupts. */
4249		- I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 \| irqs);
4250		- I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 \| irqs);
4251		-
4252		- /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
4253		- I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
4254		- I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
4255		- I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs \| irqs << 16));
4256		- I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs \| irqs << 16));
4257		- I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs \| irqs << 16));
4258		-
4259		- /*
4260		- * RPS interrupts will get enabled/disabled on demand when RPS itself
4261		- * is enabled/disabled.
4262		- */
4263		- dev_priv->pm_ier = 0x0;
4264		- dev_priv->pm_imr = ~dev_priv->pm_ier;
4265		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
4266		- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
4267		-}
4268		-
4269		-static void icp_irq_postinstall(struct drm_device *dev)
4270		-{
4271		- struct drm_i915_private *dev_priv = to_i915(dev);
4272	3472	u32 mask = SDE_GMBUS_ICP;
4273	3473
4274		- WARN_ON(I915_READ(SDEIER) != 0);
	3474	+ drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
4275	3475	I915_WRITE(SDEIER, 0xffffffff);
4276	3476	POSTING_READ(SDEIER);
4277	3477
4278		- gen3_assert_iir_is_zero(dev_priv, SDEIIR);
	3478	+ gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
4279	3479	I915_WRITE(SDEIMR, ~mask);
4280	3480
4281		- icp_hpd_detection_setup(dev_priv);
	3481	+ if (HAS_PCH_TGP(dev_priv)) {
	3482	+ icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
	3483	+ icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
	3484	+ } else if (HAS_PCH_JSP(dev_priv)) {
	3485	+ icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
	3486	+ } else if (HAS_PCH_MCC(dev_priv)) {
	3487	+ icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
	3488	+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
	3489	+ } else {
	3490	+ icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
	3491	+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
	3492	+ }
4282	3493	}
4283	3494
4284		-static int gen11_irq_postinstall(struct drm_device *dev)
	3495	+static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
4285	3496	{
4286		- struct drm_i915_private *dev_priv = dev->dev_private;
	3497	+ struct intel_uncore *uncore = &dev_priv->uncore;
4287	3498	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
4288	3499
4289		- if (HAS_PCH_ICP(dev_priv))
4290		- icp_irq_postinstall(dev);
	3500	+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
	3501	+ icp_irq_postinstall(dev_priv);
4291	3502
4292		- gen11_gt_irq_postinstall(dev_priv);
	3503	+ gen11_gt_irq_postinstall(&dev_priv->gt);
4293	3504	gen8_de_irq_postinstall(dev_priv);
4294	3505
4295		- GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
	3506	+ GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
4296	3507
4297	3508	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
4298	3509
4299		- I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
4300		- POSTING_READ(GEN11_GFX_MSTR_IRQ);
4301		-
4302		- return 0;
	3510	+ if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
	3511	+ dg1_master_intr_enable(uncore->regs);
	3512	+ POSTING_READ(DG1_MSTR_UNIT_INTR);
	3513	+ } else {
	3514	+ gen11_master_intr_enable(uncore->regs);
	3515	+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
	3516	+ }
4303	3517	}
4304	3518
4305		-static int cherryview_irq_postinstall(struct drm_device *dev)
	3519	+static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
4306	3520	{
4307		- struct drm_i915_private *dev_priv = to_i915(dev);
4308		-
4309		- gen8_gt_irq_postinstall(dev_priv);
	3521	+ gen8_gt_irq_postinstall(&dev_priv->gt);
4310	3522
4311	3523	spin_lock_irq(&dev_priv->irq_lock);
4312	3524	if (dev_priv->display_irqs_enabled)
..	..	@@ -4315,28 +3527,26 @@
4315	3527
4316	3528	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
4317	3529	POSTING_READ(GEN8_MASTER_IRQ);
4318		-
4319		- return 0;
4320	3530	}
4321	3531
4322		-static void i8xx_irq_reset(struct drm_device *dev)
	3532	+static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
4323	3533	{
4324		- struct drm_i915_private *dev_priv = to_i915(dev);
	3534	+ struct intel_uncore *uncore = &dev_priv->uncore;
4325	3535
4326	3536	i9xx_pipestat_irq_reset(dev_priv);
4327	3537
4328		- I915_WRITE16(HWSTAM, 0xffff);
4329		-
4330		- GEN2_IRQ_RESET();
	3538	+ GEN2_IRQ_RESET(uncore);
4331	3539	}
4332	3540
4333		-static int i8xx_irq_postinstall(struct drm_device *dev)
	3541	+static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
4334	3542	{
4335		- struct drm_i915_private *dev_priv = to_i915(dev);
	3543	+ struct intel_uncore *uncore = &dev_priv->uncore;
4336	3544	u16 enable_mask;
4337	3545
4338		- I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE \|
4339		- I915_ERROR_MEMORY_REFRESH));
	3546	+ intel_uncore_write16(uncore,
	3547	+ EMR,
	3548	+ ~(I915_ERROR_PAGE_TABLE \|
	3549	+ I915_ERROR_MEMORY_REFRESH));
4340	3550
4341	3551	/* Unmask the interrupts that we always want on. */
4342	3552	dev_priv->irq_mask =
..	..	@@ -4350,7 +3560,7 @@
4350	3560	I915_MASTER_ERROR_INTERRUPT \|
4351	3561	I915_USER_INTERRUPT;
4352	3562
4353		- GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
	3563	+ GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
4354	3564
4355	3565	/* Interrupt setup is already guaranteed to be single-threaded, this is
4356	3566	* just to make the assert_spin_locked check happy. */
..	..	@@ -4358,21 +3568,20 @@
4358	3568	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4359	3569	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4360	3570	spin_unlock_irq(&dev_priv->irq_lock);
4361		-
4362		- return 0;
4363	3571	}
4364	3572
4365		-static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv,
	3573	+static void i8xx_error_irq_ack(struct drm_i915_private *i915,
4366	3574	u16 eir, u16 eir_stuck)
4367	3575	{
	3576	+ struct intel_uncore *uncore = &i915->uncore;
4368	3577	u16 emr;
4369	3578
4370		- *eir = I915_READ16(EIR);
	3579	+ *eir = intel_uncore_read16(uncore, EIR);
4371	3580
4372	3581	if (*eir)
4373		- I915_WRITE16(EIR, *eir);
	3582	+ intel_uncore_write16(uncore, EIR, *eir);
4374	3583
4375		- *eir_stuck = I915_READ16(EIR);
	3584	+ *eir_stuck = intel_uncore_read16(uncore, EIR);
4376	3585	if (*eir_stuck == 0)
4377	3586	return;
4378	3587
..	..	@@ -4386,9 +3595,9 @@
4386	3595	* (or by a GPU reset) so we mask any bit that
4387	3596	* remains set.
4388	3597	*/
4389		- emr = I915_READ16(EMR);
4390		- I915_WRITE16(EMR, 0xffff);
4391		- I915_WRITE16(EMR, emr \| *eir_stuck);
	3598	+ emr = intel_uncore_read16(uncore, EMR);
	3599	+ intel_uncore_write16(uncore, EMR, 0xffff);
	3600	+ intel_uncore_write16(uncore, EMR, emr \| *eir_stuck);
4392	3601	}
4393	3602
4394	3603	static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
..	..	@@ -4397,7 +3606,8 @@
4397	3606	DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
4398	3607
4399	3608	if (eir_stuck)
4400		- DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck);
	3609	+ drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
	3610	+ eir_stuck);
4401	3611	}
4402	3612
4403	3613	static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
..	..	@@ -4434,27 +3644,27 @@
4434	3644	DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4435	3645
4436	3646	if (eir_stuck)
4437		- DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck);
	3647	+ drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
	3648	+ eir_stuck);
4438	3649	}
4439	3650
4440	3651	static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4441	3652	{
4442		- struct drm_device *dev = arg;
4443		- struct drm_i915_private *dev_priv = to_i915(dev);
	3653	+ struct drm_i915_private *dev_priv = arg;
4444	3654	irqreturn_t ret = IRQ_NONE;
4445	3655
4446	3656	if (!intel_irqs_enabled(dev_priv))
4447	3657	return IRQ_NONE;
4448	3658
4449	3659	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
4450		- disable_rpm_wakeref_asserts(dev_priv);
	3660	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4451	3661
4452	3662	do {
4453	3663	u32 pipe_stats[I915_MAX_PIPES] = {};
4454	3664	u16 eir = 0, eir_stuck = 0;
4455	3665	u16 iir;
4456	3666
4457		- iir = I915_READ16(IIR);
	3667	+ iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4458	3668	if (iir == 0)
4459	3669	break;
4460	3670
..	..	@@ -4467,10 +3677,10 @@
4467	3677	if (iir & I915_MASTER_ERROR_INTERRUPT)
4468	3678	i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4469	3679
4470		- I915_WRITE16(IIR, iir);
	3680	+ intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4471	3681
4472	3682	if (iir & I915_USER_INTERRUPT)
4473		- notify_ring(dev_priv->engine[RCS]);
	3683	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4474	3684
4475	3685	if (iir & I915_MASTER_ERROR_INTERRUPT)
4476	3686	i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
..	..	@@ -4478,14 +3688,14 @@
4478	3688	i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4479	3689	} while (0);
4480	3690
4481		- enable_rpm_wakeref_asserts(dev_priv);
	3691	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4482	3692
4483	3693	return ret;
4484	3694	}
4485	3695
4486		-static void i915_irq_reset(struct drm_device *dev)
	3696	+static void i915_irq_reset(struct drm_i915_private *dev_priv)
4487	3697	{
4488		- struct drm_i915_private *dev_priv = to_i915(dev);
	3698	+ struct intel_uncore *uncore = &dev_priv->uncore;
4489	3699
4490	3700	if (I915_HAS_HOTPLUG(dev_priv)) {
4491	3701	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
..	..	@@ -4494,14 +3704,12 @@
4494	3704
4495	3705	i9xx_pipestat_irq_reset(dev_priv);
4496	3706
4497		- I915_WRITE(HWSTAM, 0xffffffff);
4498		-
4499		- GEN3_IRQ_RESET();
	3707	+ GEN3_IRQ_RESET(uncore, GEN2_);
4500	3708	}
4501	3709
4502		-static int i915_irq_postinstall(struct drm_device *dev)
	3710	+static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4503	3711	{
4504		- struct drm_i915_private *dev_priv = to_i915(dev);
	3712	+ struct intel_uncore *uncore = &dev_priv->uncore;
4505	3713	u32 enable_mask;
4506	3714
4507	3715	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE \|
..	..	@@ -4528,7 +3736,7 @@
4528	3736	dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4529	3737	}
4530	3738
4531		- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
	3739	+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4532	3740
4533	3741	/* Interrupt setup is already guaranteed to be single-threaded, this is
4534	3742	* just to make the assert_spin_locked check happy. */
..	..	@@ -4538,21 +3746,18 @@
4538	3746	spin_unlock_irq(&dev_priv->irq_lock);
4539	3747
4540	3748	i915_enable_asle_pipestat(dev_priv);
4541		-
4542		- return 0;
4543	3749	}
4544	3750
4545	3751	static irqreturn_t i915_irq_handler(int irq, void *arg)
4546	3752	{
4547		- struct drm_device *dev = arg;
4548		- struct drm_i915_private *dev_priv = to_i915(dev);
	3753	+ struct drm_i915_private *dev_priv = arg;
4549	3754	irqreturn_t ret = IRQ_NONE;
4550	3755
4551	3756	if (!intel_irqs_enabled(dev_priv))
4552	3757	return IRQ_NONE;
4553	3758
4554	3759	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
4555		- disable_rpm_wakeref_asserts(dev_priv);
	3760	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4556	3761
4557	3762	do {
4558	3763	u32 pipe_stats[I915_MAX_PIPES] = {};
..	..	@@ -4560,7 +3765,7 @@
4560	3765	u32 hotplug_status = 0;
4561	3766	u32 iir;
4562	3767
4563		- iir = I915_READ(IIR);
	3768	+ iir = I915_READ(GEN2_IIR);
4564	3769	if (iir == 0)
4565	3770	break;
4566	3771
..	..	@@ -4577,10 +3782,10 @@
4577	3782	if (iir & I915_MASTER_ERROR_INTERRUPT)
4578	3783	i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4579	3784
4580		- I915_WRITE(IIR, iir);
	3785	+ I915_WRITE(GEN2_IIR, iir);
4581	3786
4582	3787	if (iir & I915_USER_INTERRUPT)
4583		- notify_ring(dev_priv->engine[RCS]);
	3788	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4584	3789
4585	3790	if (iir & I915_MASTER_ERROR_INTERRUPT)
4586	3791	i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
..	..	@@ -4591,28 +3796,26 @@
4591	3796	i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4592	3797	} while (0);
4593	3798
4594		- enable_rpm_wakeref_asserts(dev_priv);
	3799	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4595	3800
4596	3801	return ret;
4597	3802	}
4598	3803
4599		-static void i965_irq_reset(struct drm_device *dev)
	3804	+static void i965_irq_reset(struct drm_i915_private *dev_priv)
4600	3805	{
4601		- struct drm_i915_private *dev_priv = to_i915(dev);
	3806	+ struct intel_uncore *uncore = &dev_priv->uncore;
4602	3807
4603	3808	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4604	3809	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4605	3810
4606	3811	i9xx_pipestat_irq_reset(dev_priv);
4607	3812
4608		- I915_WRITE(HWSTAM, 0xffffffff);
4609		-
4610		- GEN3_IRQ_RESET();
	3813	+ GEN3_IRQ_RESET(uncore, GEN2_);
4611	3814	}
4612	3815
4613		-static int i965_irq_postinstall(struct drm_device *dev)
	3816	+static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4614	3817	{
4615		- struct drm_i915_private *dev_priv = to_i915(dev);
	3818	+ struct intel_uncore *uncore = &dev_priv->uncore;
4616	3819	u32 enable_mask;
4617	3820	u32 error_mask;
4618	3821
..	..	@@ -4650,7 +3853,7 @@
4650	3853	if (IS_G4X(dev_priv))
4651	3854	enable_mask \|= I915_BSD_USER_INTERRUPT;
4652	3855
4653		- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
	3856	+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4654	3857
4655	3858	/* Interrupt setup is already guaranteed to be single-threaded, this is
4656	3859	* just to make the assert_spin_locked check happy. */
..	..	@@ -4661,8 +3864,6 @@
4661	3864	spin_unlock_irq(&dev_priv->irq_lock);
4662	3865
4663	3866	i915_enable_asle_pipestat(dev_priv);
4664		-
4665		- return 0;
4666	3867	}
4667	3868
4668	3869	static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
..	..	@@ -4692,15 +3893,14 @@
4692	3893
4693	3894	static irqreturn_t i965_irq_handler(int irq, void *arg)
4694	3895	{
4695		- struct drm_device *dev = arg;
4696		- struct drm_i915_private *dev_priv = to_i915(dev);
	3896	+ struct drm_i915_private *dev_priv = arg;
4697	3897	irqreturn_t ret = IRQ_NONE;
4698	3898
4699	3899	if (!intel_irqs_enabled(dev_priv))
4700	3900	return IRQ_NONE;
4701	3901
4702	3902	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
4703		- disable_rpm_wakeref_asserts(dev_priv);
	3903	+ disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4704	3904
4705	3905	do {
4706	3906	u32 pipe_stats[I915_MAX_PIPES] = {};
..	..	@@ -4708,7 +3908,7 @@
4708	3908	u32 hotplug_status = 0;
4709	3909	u32 iir;
4710	3910
4711		- iir = I915_READ(IIR);
	3911	+ iir = I915_READ(GEN2_IIR);
4712	3912	if (iir == 0)
4713	3913	break;
4714	3914
..	..	@@ -4724,13 +3924,13 @@
4724	3924	if (iir & I915_MASTER_ERROR_INTERRUPT)
4725	3925	i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4726	3926
4727		- I915_WRITE(IIR, iir);
	3927	+ I915_WRITE(GEN2_IIR, iir);
4728	3928
4729	3929	if (iir & I915_USER_INTERRUPT)
4730		- notify_ring(dev_priv->engine[RCS]);
	3930	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
4731	3931
4732	3932	if (iir & I915_BSD_USER_INTERRUPT)
4733		- notify_ring(dev_priv->engine[VCS]);
	3933	+ intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
4734	3934
4735	3935	if (iir & I915_MASTER_ERROR_INTERRUPT)
4736	3936	i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
..	..	@@ -4741,7 +3941,7 @@
4741	3941	i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4742	3942	} while (0);
4743	3943
4744		- enable_rpm_wakeref_asserts(dev_priv);
	3944	+ enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4745	3945
4746	3946	return ret;
4747	3947	}
..	..	@@ -4756,59 +3956,21 @@
4756	3956	void intel_irq_init(struct drm_i915_private *dev_priv)
4757	3957	{
4758	3958	struct drm_device *dev = &dev_priv->drm;
4759		- struct intel_rps *rps = &dev_priv->gt_pm.rps;
4760	3959	int i;
	3960	+
	3961	+ intel_hpd_init_pins(dev_priv);
4761	3962
4762	3963	intel_hpd_init_work(dev_priv);
4763	3964
4764		- INIT_WORK(&rps->work, gen6_pm_rps_work);
4765		-
4766		- INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
	3965	+ INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4767	3966	for (i = 0; i < MAX_L3_SLICES; ++i)
4768	3967	dev_priv->l3_parity.remap_info[i] = NULL;
4769	3968
4770		- if (HAS_GUC_SCHED(dev_priv))
4771		- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
	3969	+ /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
	3970	+ if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
	3971	+ dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4772	3972
4773		- /* Let's track the enabled rps events */
4774		- if (IS_VALLEYVIEW(dev_priv))
4775		- /* WaGsvRC0ResidencyMethod:vlv */
4776		- dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4777		- else
4778		- dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4779		-
4780		- rps->pm_intrmsk_mbz = 0;
4781		-
4782		- /*
4783		- * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4784		- * if GEN6_PM_UP_EI_EXPIRED is masked.
4785		- *
4786		- * TODO: verify if this can be reproduced on VLV,CHV.
4787		- */
4788		- if (INTEL_GEN(dev_priv) <= 7)
4789		- rps->pm_intrmsk_mbz \|= GEN6_PM_RP_UP_EI_EXPIRED;
4790		-
4791		- if (INTEL_GEN(dev_priv) >= 8)
4792		- rps->pm_intrmsk_mbz \|= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4793		-
4794		- if (IS_GEN2(dev_priv)) {
4795		- /* Gen2 doesn't have a hardware frame counter */
4796		- dev->max_vblank_count = 0;
4797		- } else if (IS_G4X(dev_priv) \|\| INTEL_GEN(dev_priv) >= 5) {
4798		- dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4799		- dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4800		- } else {
4801		- dev->driver->get_vblank_counter = i915_get_vblank_counter;
4802		- dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4803		- }
4804		-
4805		- /*
4806		- * Opt out of the vblank disable timer on everything except gen2.
4807		- * Gen2 doesn't have a hardware frame counter and so depends on
4808		- * vblank interrupts to produce sane vblank seuquence numbers.
4809		- */
4810		- if (!IS_GEN2(dev_priv))
4811		- dev->vblank_disable_immediate = true;
	3973	+ dev->vblank_disable_immediate = true;
4812	3974
4813	3975	/* Most platforms treat the display irq block as an always-on
4814	3976	* power domain. vlv/chv can disable it at runtime and need
..	..	@@ -4821,81 +3983,30 @@
4821	3983	dev_priv->display_irqs_enabled = false;
4822	3984
4823	3985	dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
	3986	+ /* If we have MST support, we want to avoid doing short HPD IRQ storm
	3987	+ * detection, as short HPD storms will occur as a natural part of
	3988	+ * sideband messaging with MST.
	3989	+ * On older platforms however, IRQ storms can occur with both long and
	3990	+ * short pulses, as seen on some G4x systems.
	3991	+ */
	3992	+ dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4824	3993
4825		- dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
4826		- dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4827		-
4828		- if (IS_CHERRYVIEW(dev_priv)) {
4829		- dev->driver->irq_handler = cherryview_irq_handler;
4830		- dev->driver->irq_preinstall = cherryview_irq_reset;
4831		- dev->driver->irq_postinstall = cherryview_irq_postinstall;
4832		- dev->driver->irq_uninstall = cherryview_irq_reset;
4833		- dev->driver->enable_vblank = i965_enable_vblank;
4834		- dev->driver->disable_vblank = i965_disable_vblank;
4835		- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4836		- } else if (IS_VALLEYVIEW(dev_priv)) {
4837		- dev->driver->irq_handler = valleyview_irq_handler;
4838		- dev->driver->irq_preinstall = valleyview_irq_reset;
4839		- dev->driver->irq_postinstall = valleyview_irq_postinstall;
4840		- dev->driver->irq_uninstall = valleyview_irq_reset;
4841		- dev->driver->enable_vblank = i965_enable_vblank;
4842		- dev->driver->disable_vblank = i965_disable_vblank;
4843		- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4844		- } else if (INTEL_GEN(dev_priv) >= 11) {
4845		- dev->driver->irq_handler = gen11_irq_handler;
4846		- dev->driver->irq_preinstall = gen11_irq_reset;
4847		- dev->driver->irq_postinstall = gen11_irq_postinstall;
4848		- dev->driver->irq_uninstall = gen11_irq_reset;
4849		- dev->driver->enable_vblank = gen8_enable_vblank;
4850		- dev->driver->disable_vblank = gen8_disable_vblank;
4851		- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4852		- } else if (INTEL_GEN(dev_priv) >= 8) {
4853		- dev->driver->irq_handler = gen8_irq_handler;
4854		- dev->driver->irq_preinstall = gen8_irq_reset;
4855		- dev->driver->irq_postinstall = gen8_irq_postinstall;
4856		- dev->driver->irq_uninstall = gen8_irq_reset;
4857		- dev->driver->enable_vblank = gen8_enable_vblank;
4858		- dev->driver->disable_vblank = gen8_disable_vblank;
4859		- if (IS_GEN9_LP(dev_priv))
	3994	+ if (HAS_GMCH(dev_priv)) {
	3995	+ if (I915_HAS_HOTPLUG(dev_priv))
	3996	+ dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
	3997	+ } else {
	3998	+ if (HAS_PCH_JSP(dev_priv))
	3999	+ dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
	4000	+ else if (HAS_PCH_MCC(dev_priv))
	4001	+ dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
	4002	+ else if (INTEL_GEN(dev_priv) >= 11)
	4003	+ dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
	4004	+ else if (IS_GEN9_LP(dev_priv))
4860	4005	dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4861		- else if (HAS_PCH_SPT(dev_priv) \|\| HAS_PCH_KBP(dev_priv) \|\|
4862		- HAS_PCH_CNP(dev_priv))
	4006	+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4863	4007	dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4864	4008	else
4865	4009	dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4866		- } else if (HAS_PCH_SPLIT(dev_priv)) {
4867		- dev->driver->irq_handler = ironlake_irq_handler;
4868		- dev->driver->irq_preinstall = ironlake_irq_reset;
4869		- dev->driver->irq_postinstall = ironlake_irq_postinstall;
4870		- dev->driver->irq_uninstall = ironlake_irq_reset;
4871		- dev->driver->enable_vblank = ironlake_enable_vblank;
4872		- dev->driver->disable_vblank = ironlake_disable_vblank;
4873		- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4874		- } else {
4875		- if (IS_GEN2(dev_priv)) {
4876		- dev->driver->irq_preinstall = i8xx_irq_reset;
4877		- dev->driver->irq_postinstall = i8xx_irq_postinstall;
4878		- dev->driver->irq_handler = i8xx_irq_handler;
4879		- dev->driver->irq_uninstall = i8xx_irq_reset;
4880		- dev->driver->enable_vblank = i8xx_enable_vblank;
4881		- dev->driver->disable_vblank = i8xx_disable_vblank;
4882		- } else if (IS_GEN3(dev_priv)) {
4883		- dev->driver->irq_preinstall = i915_irq_reset;
4884		- dev->driver->irq_postinstall = i915_irq_postinstall;
4885		- dev->driver->irq_uninstall = i915_irq_reset;
4886		- dev->driver->irq_handler = i915_irq_handler;
4887		- dev->driver->enable_vblank = i8xx_enable_vblank;
4888		- dev->driver->disable_vblank = i8xx_disable_vblank;
4889		- } else {
4890		- dev->driver->irq_preinstall = i965_irq_reset;
4891		- dev->driver->irq_postinstall = i965_irq_postinstall;
4892		- dev->driver->irq_uninstall = i965_irq_reset;
4893		- dev->driver->irq_handler = i965_irq_handler;
4894		- dev->driver->enable_vblank = i965_enable_vblank;
4895		- dev->driver->disable_vblank = i965_disable_vblank;
4896		- }
4897		- if (I915_HAS_HOTPLUG(dev_priv))
4898		- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4899	4010	}
4900	4011	}
4901	4012
..	..	@@ -4913,6 +4024,77 @@
4913	4024	kfree(i915->l3_parity.remap_info[i]);
4914	4025	}
4915	4026
	4027	+static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
	4028	+{
	4029	+ if (HAS_GMCH(dev_priv)) {
	4030	+ if (IS_CHERRYVIEW(dev_priv))
	4031	+ return cherryview_irq_handler;
	4032	+ else if (IS_VALLEYVIEW(dev_priv))
	4033	+ return valleyview_irq_handler;
	4034	+ else if (IS_GEN(dev_priv, 4))
	4035	+ return i965_irq_handler;
	4036	+ else if (IS_GEN(dev_priv, 3))
	4037	+ return i915_irq_handler;
	4038	+ else
	4039	+ return i8xx_irq_handler;
	4040	+ } else {
	4041	+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
	4042	+ return dg1_irq_handler;
	4043	+ if (INTEL_GEN(dev_priv) >= 11)
	4044	+ return gen11_irq_handler;
	4045	+ else if (INTEL_GEN(dev_priv) >= 8)
	4046	+ return gen8_irq_handler;
	4047	+ else
	4048	+ return ilk_irq_handler;
	4049	+ }
	4050	+}
	4051	+
	4052	+static void intel_irq_reset(struct drm_i915_private *dev_priv)
	4053	+{
	4054	+ if (HAS_GMCH(dev_priv)) {
	4055	+ if (IS_CHERRYVIEW(dev_priv))
	4056	+ cherryview_irq_reset(dev_priv);
	4057	+ else if (IS_VALLEYVIEW(dev_priv))
	4058	+ valleyview_irq_reset(dev_priv);
	4059	+ else if (IS_GEN(dev_priv, 4))
	4060	+ i965_irq_reset(dev_priv);
	4061	+ else if (IS_GEN(dev_priv, 3))
	4062	+ i915_irq_reset(dev_priv);
	4063	+ else
	4064	+ i8xx_irq_reset(dev_priv);
	4065	+ } else {
	4066	+ if (INTEL_GEN(dev_priv) >= 11)
	4067	+ gen11_irq_reset(dev_priv);
	4068	+ else if (INTEL_GEN(dev_priv) >= 8)
	4069	+ gen8_irq_reset(dev_priv);
	4070	+ else
	4071	+ ilk_irq_reset(dev_priv);
	4072	+ }
	4073	+}
	4074	+
	4075	+static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
	4076	+{
	4077	+ if (HAS_GMCH(dev_priv)) {
	4078	+ if (IS_CHERRYVIEW(dev_priv))
	4079	+ cherryview_irq_postinstall(dev_priv);
	4080	+ else if (IS_VALLEYVIEW(dev_priv))
	4081	+ valleyview_irq_postinstall(dev_priv);
	4082	+ else if (IS_GEN(dev_priv, 4))
	4083	+ i965_irq_postinstall(dev_priv);
	4084	+ else if (IS_GEN(dev_priv, 3))
	4085	+ i915_irq_postinstall(dev_priv);
	4086	+ else
	4087	+ i8xx_irq_postinstall(dev_priv);
	4088	+ } else {
	4089	+ if (INTEL_GEN(dev_priv) >= 11)
	4090	+ gen11_irq_postinstall(dev_priv);
	4091	+ else if (INTEL_GEN(dev_priv) >= 8)
	4092	+ gen8_irq_postinstall(dev_priv);
	4093	+ else
	4094	+ ilk_irq_postinstall(dev_priv);
	4095	+ }
	4096	+}
	4097	+
4916	4098	/**
4917	4099	* intel_irq_install - enables the hardware interrupt
4918	4100	* @dev_priv: i915 device instance
..	..	@@ -4926,6 +4108,9 @@
4926	4108	*/
4927	4109	int intel_irq_install(struct drm_i915_private *dev_priv)
4928	4110	{
	4111	+ int irq = dev_priv->drm.pdev->irq;
	4112	+ int ret;
	4113	+
4929	4114	/*
4930	4115	* We enable some interrupt sources in our postinstall hooks, so mark
4931	4116	* interrupts as enabled _before_ actually enabling them to avoid
..	..	@@ -4933,7 +4118,20 @@
4933	4118	*/
4934	4119	dev_priv->runtime_pm.irqs_enabled = true;
4935	4120
4936		- return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
	4121	+ dev_priv->drm.irq_enabled = true;
	4122	+
	4123	+ intel_irq_reset(dev_priv);
	4124	+
	4125	+ ret = request_irq(irq, intel_irq_handler(dev_priv),
	4126	+ IRQF_SHARED, DRIVER_NAME, dev_priv);
	4127	+ if (ret < 0) {
	4128	+ dev_priv->drm.irq_enabled = false;
	4129	+ return ret;
	4130	+ }
	4131	+
	4132	+ intel_irq_postinstall(dev_priv);
	4133	+
	4134	+ return ret;
4937	4135	}
4938	4136
4939	4137	/**
..	..	@@ -4945,7 +4143,23 @@
4945	4143	*/
4946	4144	void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4947	4145	{
4948		- drm_irq_uninstall(&dev_priv->drm);
	4146	+ int irq = dev_priv->drm.pdev->irq;
	4147	+
	4148	+ /*
	4149	+ * FIXME we can get called twice during driver probe
	4150	+ * error handling as well as during driver remove due to
	4151	+ * intel_modeset_driver_remove() calling us out of sequence.
	4152	+ * Would be nice if it didn't do that...
	4153	+ */
	4154	+ if (!dev_priv->drm.irq_enabled)
	4155	+ return;
	4156	+
	4157	+ dev_priv->drm.irq_enabled = false;
	4158	+
	4159	+ intel_irq_reset(dev_priv);
	4160	+
	4161	+ free_irq(irq, dev_priv);
	4162	+
4949	4163	intel_hpd_cancel_work(dev_priv);
4950	4164	dev_priv->runtime_pm.irqs_enabled = false;
4951	4165	}
..	..	@@ -4959,9 +4173,9 @@
4959	4173	*/
4960	4174	void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4961	4175	{
4962		- dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
	4176	+ intel_irq_reset(dev_priv);
4963	4177	dev_priv->runtime_pm.irqs_enabled = false;
4964		- synchronize_irq(dev_priv->drm.irq);
	4178	+ intel_synchronize_irq(dev_priv);
4965	4179	}
4966	4180
4967	4181	/**
..	..	@@ -4974,6 +4188,20 @@
4974	4188	void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4975	4189	{
4976	4190	dev_priv->runtime_pm.irqs_enabled = true;
4977		- dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4978		- dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
	4191	+ intel_irq_reset(dev_priv);
	4192	+ intel_irq_postinstall(dev_priv);
	4193	+}
	4194	+
	4195	+bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
	4196	+{
	4197	+ /*
	4198	+ * We only use drm_irq_uninstall() at unload and VT switch, so
	4199	+ * this is the only thing we need to check.
	4200	+ */
	4201	+ return dev_priv->runtime_pm.irqs_enabled;
	4202	+}
	4203	+
	4204	+void intel_synchronize_irq(struct drm_i915_private *i915)
	4205	+{
	4206	+ synchronize_irq(i915->drm.pdev->irq);
4979	4207	}