forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
....@@ -54,6 +54,7 @@
5454 	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
5555 	SRI(OTG_STEREO_STATUS, OTG, inst),\
5656 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
57
+	SRI(OTG_V_TOTAL_MID, OTG, inst),\
5758 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
5859 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
5960 	SRI(OTG_TRIGA_CNTL, OTG, inst),\
....@@ -67,6 +68,8 @@
6768 	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
6869 	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
6970 	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
71
+	SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
72
+	SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
7073 	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
7174 	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
7275 	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
....@@ -82,13 +85,17 @@
8285 	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
8386 	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
8487 	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
85
-	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst)
88
+	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
89
+	SR(GSL_SOURCE_SELECT),\
90
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
91
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
8692 
8793 #define TG_COMMON_REG_LIST_DCN1_0(inst) \
8894 	TG_COMMON_REG_LIST_DCN(inst),\
8995 	SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
9096 	SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
91
-	SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
97
+	SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
98
+	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
9299 
93100 
94101 struct dcn_optc_registers {
....@@ -119,9 +126,12 @@
119126 	uint32_t OTG_3D_STRUCTURE_CONTROL;
120127 	uint32_t OTG_STEREO_STATUS;
121128 	uint32_t OTG_V_TOTAL_MAX;
129
+	uint32_t OTG_V_TOTAL_MID;
122130 	uint32_t OTG_V_TOTAL_MIN;
123131 	uint32_t OTG_V_TOTAL_CONTROL;
124132 	uint32_t OTG_TRIGA_CNTL;
133
+	uint32_t OTG_TRIGA_MANUAL_TRIG;
134
+	uint32_t OTG_MANUAL_FLOW_CONTROL;
125135 	uint32_t OTG_FORCE_COUNT_NOW_CNTL;
126136 	uint32_t OTG_STATIC_SCREEN_CONTROL;
127137 	uint32_t OTG_STATUS_FRAME_COUNT;
....@@ -135,6 +145,8 @@
135145 	uint32_t OTG_CLOCK_CONTROL;
136146 	uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
137147 	uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
148
+	uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL;
149
+	uint32_t OTG_VERTICAL_INTERRUPT1_POSITION;
138150 	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
139151 	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
140152 	uint32_t OPTC_INPUT_CLOCK_CONTROL;
....@@ -146,12 +158,28 @@
146158 	uint32_t OTG_GSL_WINDOW_Y;
147159 	uint32_t OTG_VUPDATE_KEEPOUT;
148160 	uint32_t OTG_CRC_CNTL;
161
+	uint32_t OTG_CRC_CNTL2;
149162 	uint32_t OTG_CRC0_DATA_RG;
150163 	uint32_t OTG_CRC0_DATA_B;
151164 	uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
152165 	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
153166 	uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
154167 	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
168
+	uint32_t GSL_SOURCE_SELECT;
169
+	uint32_t DWB_SOURCE_SELECT;
170
+	uint32_t OTG_DSC_START_POSITION;
171
+	uint32_t OPTC_DATA_FORMAT_CONTROL;
172
+	uint32_t OPTC_BYTES_PER_PIXEL;
173
+	uint32_t OPTC_WIDTH_CONTROL;
174
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
175
+	uint32_t OTG_BLANK_DATA_COLOR;
176
+	uint32_t OTG_BLANK_DATA_COLOR_EXT;
177
+	uint32_t OTG_DRR_TRIGGER_WINDOW;
178
+	uint32_t OTG_M_CONST_DTO0;
179
+	uint32_t OTG_M_CONST_DTO1;
180
+	uint32_t OTG_DRR_V_TOTAL_CHANGE;
181
+	uint32_t OTG_GLOBAL_CONTROL4;
182
+#endif
155183 };
156184 
157185 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
....@@ -167,6 +195,7 @@
167195 	SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
168196 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
169197 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
198
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
170199 	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
171200 	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
172201 	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
....@@ -196,12 +225,15 @@
196225 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
197226 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
198227 	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
228
+	SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
199229 	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
200230 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
201231 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
202232 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
203233 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
204234 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
235
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
236
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
205237 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
206238 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
207239 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
....@@ -209,6 +241,11 @@
209241 	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
210242 	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
211243 	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
244
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
245
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
246
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
247
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
248
+	SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
212249 	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
213250 	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
214251 	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
....@@ -227,6 +264,8 @@
227264 	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
228265 	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
229266 	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
267
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
268
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
230269 	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
231270 	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
232271 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
....@@ -260,7 +299,12 @@
260299 	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
261300 	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
262301 	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
263
-	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh)
302
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
303
+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
304
+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
305
+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
306
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
307
+
264308 
265309 
266310 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
....@@ -276,7 +320,8 @@
276320 	SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
277321 	SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
278322 	SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
279
-	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh)
323
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
324
+	SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\
280325 
281326 #define TG_REG_FIELD_LIST_DCN1_0(type) \
282327 	type VSTARTUP_START;\
....@@ -319,9 +364,12 @@
319364 	type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
320365 	type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
321366 	type OTG_V_TOTAL_MAX;\
367
+	type OTG_V_TOTAL_MID;\
322368 	type OTG_V_TOTAL_MIN;\
323369 	type OTG_V_TOTAL_MIN_SEL;\
324370 	type OTG_V_TOTAL_MAX_SEL;\
371
+	type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
372
+	type OTG_VTOTAL_MID_FRAME_NUM;\
325373 	type OTG_FORCE_LOCK_ON_EVENT;\
326374 	type OTG_SET_V_TOTAL_MIN_MASK_EN;\
327375 	type OTG_SET_V_TOTAL_MIN_MASK;\
....@@ -332,6 +380,11 @@
332380 	type OTG_TRIGA_SOURCE_PIPE_SELECT;\
333381 	type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
334382 	type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
383
+	type OTG_TRIGA_POLARITY_SELECT;\
384
+	type OTG_TRIGA_FREQUENCY_SELECT;\
385
+	type OTG_TRIGA_DELAY;\
386
+	type OTG_TRIGA_CLEAR;\
387
+	type OTG_TRIGA_MANUAL_TRIG;\
335388 	type OTG_STATIC_SCREEN_EVENT_MASK;\
336389 	type OTG_STATIC_SCREEN_FRAME_COUNT;\
337390 	type OTG_FRAME_COUNT;\
....@@ -343,6 +396,13 @@
343396 	type OTG_BLACK_COLOR_B_CB;\
344397 	type OTG_BLACK_COLOR_G_Y;\
345398 	type OTG_BLACK_COLOR_R_CR;\
399
+	type OTG_BLANK_DATA_COLOR_BLUE_CB;\
400
+	type OTG_BLANK_DATA_COLOR_GREEN_Y;\
401
+	type OTG_BLANK_DATA_COLOR_RED_CR;\
402
+	type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\
403
+	type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\
404
+	type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\
405
+	type OTG_VTOTAL_MID_REPLACING_MIN_EN;\
346406 	type OTG_TEST_PATTERN_INC0;\
347407 	type OTG_TEST_PATTERN_INC1;\
348408 	type OTG_TEST_PATTERN_VRES;\
....@@ -361,6 +421,8 @@
361421 	type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
362422 	type OTG_VERTICAL_INTERRUPT0_LINE_START;\
363423 	type OTG_VERTICAL_INTERRUPT0_LINE_END;\
424
+	type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\
425
+	type OTG_VERTICAL_INTERRUPT1_LINE_START;\
364426 	type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
365427 	type OTG_VERTICAL_INTERRUPT2_LINE_START;\
366428 	type OPTC_INPUT_CLK_EN;\
....@@ -405,11 +467,83 @@
405467 	type OTG_CRC0_WINDOWB_X_START;\
406468 	type OTG_CRC0_WINDOWB_X_END;\
407469 	type OTG_CRC0_WINDOWB_Y_START;\
408
-	type OTG_CRC0_WINDOWB_Y_END;
470
+	type OTG_CRC0_WINDOWB_Y_END;\
471
+	type GSL0_READY_SOURCE_SEL;\
472
+	type GSL1_READY_SOURCE_SEL;\
473
+	type GSL2_READY_SOURCE_SEL;\
474
+	type MANUAL_FLOW_CONTROL;\
475
+	type MANUAL_FLOW_CONTROL_SEL;
409476 
477
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
410478 
411479 #define TG_REG_FIELD_LIST(type) \
412
-	TG_REG_FIELD_LIST_DCN1_0(type)
480
+	TG_REG_FIELD_LIST_DCN1_0(type)\
481
+	type OTG_V_SYNC_MODE;\
482
+	type OTG_DRR_TRIGGER_WINDOW_START_X;\
483
+	type OTG_DRR_TRIGGER_WINDOW_END_X;\
484
+	type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\
485
+	type OTG_OUT_MUX;\
486
+	type OTG_M_CONST_DTO_PHASE;\
487
+	type OTG_M_CONST_DTO_MODULO;\
488
+	type MASTER_UPDATE_LOCK_DB_X;\
489
+	type MASTER_UPDATE_LOCK_DB_Y;\
490
+	type MASTER_UPDATE_LOCK_DB_EN;\
491
+	type GLOBAL_UPDATE_LOCK_EN;\
492
+	type DIG_UPDATE_LOCATION;\
493
+	type OTG_DSC_START_POSITION_X;\
494
+	type OTG_DSC_START_POSITION_LINE_NUM;\
495
+	type OPTC_NUM_OF_INPUT_SEGMENT;\
496
+	type OPTC_SEG0_SRC_SEL;\
497
+	type OPTC_SEG1_SRC_SEL;\
498
+	type OPTC_SEG2_SRC_SEL;\
499
+	type OPTC_SEG3_SRC_SEL;\
500
+	type OPTC_MEM_SEL;\
501
+	type OPTC_DATA_FORMAT;\
502
+	type OPTC_DSC_MODE;\
503
+	type OPTC_DSC_BYTES_PER_PIXEL;\
504
+	type OPTC_DSC_SLICE_WIDTH;\
505
+	type OPTC_SEGMENT_WIDTH;\
506
+	type OPTC_DWB0_SOURCE_SELECT;\
507
+	type OPTC_DWB1_SOURCE_SELECT;\
508
+	type MASTER_UPDATE_LOCK_DB_START_X;\
509
+	type MASTER_UPDATE_LOCK_DB_END_X;\
510
+	type MASTER_UPDATE_LOCK_DB_START_Y;\
511
+	type MASTER_UPDATE_LOCK_DB_END_Y;\
512
+	type DIG_UPDATE_POSITION_X;\
513
+	type DIG_UPDATE_POSITION_Y;\
514
+	type OTG_H_TIMING_DIV_MODE;\
515
+	type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
516
+	type OTG_CRC_DSC_MODE;\
517
+	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
518
+	type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
519
+	type OTG_CRC_DATA_FORMAT;
520
+#else
521
+
522
+#define TG_REG_FIELD_LIST(type) \
523
+	TG_REG_FIELD_LIST_DCN1_0(type)\
524
+	type MASTER_UPDATE_LOCK_DB_X;\
525
+	type MASTER_UPDATE_LOCK_DB_Y;\
526
+	type MASTER_UPDATE_LOCK_DB_EN;\
527
+	type GLOBAL_UPDATE_LOCK_EN;\
528
+	type DIG_UPDATE_LOCATION;\
529
+	type OTG_DSC_START_POSITION_X;\
530
+	type OTG_DSC_START_POSITION_LINE_NUM;\
531
+	type OPTC_NUM_OF_INPUT_SEGMENT;\
532
+	type OPTC_SEG0_SRC_SEL;\
533
+	type OPTC_SEG1_SRC_SEL;\
534
+	type OPTC_MEM_SEL;\
535
+	type OPTC_DATA_FORMAT;\
536
+	type OPTC_DSC_MODE;\
537
+	type OPTC_DSC_BYTES_PER_PIXEL;\
538
+	type OPTC_DSC_SLICE_WIDTH;\
539
+	type OPTC_SEGMENT_WIDTH;\
540
+	type OPTC_DWB0_SOURCE_SELECT;\
541
+	type OPTC_DWB1_SOURCE_SELECT;\
542
+	type OTG_CRC_DSC_MODE;\
543
+	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
544
+	type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
545
+	type OTG_CRC_DATA_FORMAT;
546
+#endif
413547 
414548 
415549 struct dcn_optc_shift {
....@@ -427,7 +561,7 @@
427561 	const struct dcn_optc_shift *tg_shift;
428562 	const struct dcn_optc_mask *tg_mask;
429563 
430
-	enum controller_id controller_id;
564
+	int opp_count;
431565 
432566 	uint32_t max_h_total;
433567 	uint32_t max_v_total;
....@@ -438,6 +572,12 @@
438572 	uint32_t min_v_sync_width;
439573 	uint32_t min_v_blank;
440574 	uint32_t min_v_blank_interlace;
575
+
576
+	int vstartup_start;
577
+	int vupdate_offset;
578
+	int vupdate_width;
579
+	int vready_offset;
580
+	enum signal_type signal;
441581 };
442582 
443583 void dcn10_timing_generator_init(struct optc *optc);
....@@ -461,10 +601,14 @@
461601 	uint32_t h_total;
462602 	uint32_t underflow_occurred_status;
463603 	uint32_t otg_enabled;
604
+	uint32_t blank_enabled;
464605 };
465606 
466607 void optc1_read_otg_state(struct optc *optc1,
467608 		struct dcn_otg_state *s);
609
+
610
+bool optc1_get_hw_timing(struct timing_generator *tg,
611
+		struct dc_crtc_timing *hw_crtc_timing);
468612 
469613 bool optc1_validate_timing(
470614 	struct timing_generator *optc,
....@@ -473,14 +617,30 @@
473617 void optc1_program_timing(
474618 	struct timing_generator *optc,
475619 	const struct dc_crtc_timing *dc_crtc_timing,
620
+	int vready_offset,
621
+	int vstartup_start,
622
+	int vupdate_offset,
623
+	int vupdate_width,
624
+	const enum signal_type signal,
476625 	bool use_vbios);
477626 
478
-void optc1_program_vline_interrupt(struct timing_generator *optc,
479
-		const struct dc_crtc_timing *dc_crtc_timing,
480
-		unsigned long long vsync_delta);
627
+void optc1_setup_vertical_interrupt0(
628
+		struct timing_generator *optc,
629
+		uint32_t start_line,
630
+		uint32_t end_line);
631
+void optc1_setup_vertical_interrupt1(
632
+		struct timing_generator *optc,
633
+		uint32_t start_line);
634
+void optc1_setup_vertical_interrupt2(
635
+		struct timing_generator *optc,
636
+		uint32_t start_line);
481637 
482638 void optc1_program_global_sync(
483
-		struct timing_generator *optc);
639
+		struct timing_generator *optc,
640
+		int vready_offset,
641
+		int vstartup_start,
642
+		int vupdate_offset,
643
+		int vupdate_width);
484644 
485645 bool optc1_disable_crtc(struct timing_generator *optc);
486646 
....@@ -533,7 +693,8 @@
533693 
534694 void optc1_set_static_screen_control(
535695 	struct timing_generator *optc,
536
-	uint32_t value);
696
+	uint32_t event_triggers,
697
+	uint32_t num_frames);
537698 
538699 void optc1_program_stereo(struct timing_generator *optc,
539700 	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
....@@ -550,6 +711,8 @@
550711 
551712 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
552713 
714
+void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
715
+
553716 bool optc1_get_otg_active_size(struct timing_generator *optc,
554717 		uint32_t *otg_active_width,
555718 		uint32_t *otg_active_height);
....@@ -565,4 +728,9 @@
565728 bool optc1_get_crc(struct timing_generator *optc,
566729 		    uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
567730 
731
+bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
732
+
733
+void optc1_set_vtg_params(struct timing_generator *optc,
734
+		const struct dc_crtc_timing *dc_crtc_timing);
735
+
568736 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */