change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
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@@ -51,10 +51,6 @@
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 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
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-struct dcn10_input_csc_matrix {
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-	enum dc_color_space color_space;
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-	uint16_t regval[12];
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-};
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 enum dcn10_coef_filter_type_sel {
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 	SCL_COEF_LUMA_VERT_FILTER = 0,
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@@ -90,33 +86,6 @@
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 	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
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 	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
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 	DSCL_MODE_DSCL_BYPASS = 6
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-};
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-
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-enum gamut_remap_select {
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-	GAMUT_REMAP_BYPASS = 0,
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-	GAMUT_REMAP_COEFF,
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-	GAMUT_REMAP_COMA_COEFF,
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-	GAMUT_REMAP_COMB_COEFF
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-};
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-
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-static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
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-	{COLOR_SPACE_SRGB,
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-		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
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-	{COLOR_SPACE_SRGB_LIMITED,
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-		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
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-	{COLOR_SPACE_YCBCR601,
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-		{0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
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-						0, 0x2000, 0x38b4, 0xe3a6} },
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-	{COLOR_SPACE_YCBCR601_LIMITED,
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-		{0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
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-						0, 0x2568, 0x40de, 0xdd3a} },
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-	{COLOR_SPACE_YCBCR709,
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-		{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
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-						0x2000, 0x3b61, 0xe24f} },
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-
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-	{COLOR_SPACE_YCBCR709_LIMITED,
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-		{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
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-						0x2568, 0x43ee, 0xdbb2} }
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 };
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 static void program_gamut_remap(
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@@ -363,6 +332,8 @@
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 	uint32_t i;
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 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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+	REG_SEQ_START();
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+
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 	for (i = 0 ; i < num; i++) {
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 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
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 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
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@@ -454,7 +425,7 @@
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 {
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 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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 	int i;
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-	int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
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+	int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
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 	const uint16_t *regval = NULL;
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 	uint32_t cur_select = 0;
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 	enum dcn10_input_csc_select select;
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@@ -467,8 +438,8 @@
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 	if (tbl_entry == NULL) {
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 		for (i = 0; i < arr_size; i++)
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-			if (dcn10_input_csc_matrix[i].color_space == color_space) {
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-				regval = dcn10_input_csc_matrix[i].regval;
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+			if (dpp_input_csc_matrix[i].color_space == color_space) {
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+				regval = dpp_input_csc_matrix[i].regval;
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 				break;
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 			}
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@@ -637,10 +608,16 @@
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 	case IPP_DEGAMMA_MODE_HW_xvYCC:
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 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
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 			break;
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+	case IPP_DEGAMMA_MODE_USER_PWL:
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+		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
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+		break;
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 	default:
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 		BREAK_TO_DEBUGGER();
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 		break;
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 	}
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+
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+	REG_SEQ_SUBMIT();
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+	REG_SEQ_WAIT_DONE();
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 }
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 void dpp1_degamma_ram_select(
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@@ -742,6 +719,8 @@
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 	/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
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 	if (dpp->tf_mask->CM_BYPASS_EN)
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 		REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
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+	else
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+		REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
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 	/* Setting degamma bypass for now */
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 	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);