change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/crypto/qce/common.c
..
..
@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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5
 
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 #include <linux/err.h>
..
..
@@ -22,8 +14,6 @@
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 #include "core.h"
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 #include "regs-v5.h"
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 #include "sha.h"
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-
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-#define QCE_SECTOR_SIZE		512
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17
 
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 static inline u32 qce_read(struct qce_device *qce, u32 offset)
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 {
..
..
@@ -53,52 +43,56 @@
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 		qce_write(qce, offset + i * sizeof(u32), 0);
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 }
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45
 
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-static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
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+static u32 qce_config_reg(struct qce_device *qce, int little)
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 {
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-	u32 cfg = 0;
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+	u32 beats = (qce->burst_size >> 3) - 1;
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+	u32 pipe_pair = qce->pipe_pair_id;
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+	u32 config;
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51
 
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-	if (IS_AES(flags)) {
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-		if (aes_key_size == AES_KEYSIZE_128)
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-			cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
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-		else if (aes_key_size == AES_KEYSIZE_256)
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-			cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
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-	}
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+	config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
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+	config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
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+		  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
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+	config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
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+	config &= ~HIGH_SPD_EN_N_SHIFT;
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57
 
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-	if (IS_AES(flags))
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-		cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
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-	else if (IS_DES(flags) || IS_3DES(flags))
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-		cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
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+	if (little)
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+		config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
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60
 
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-	if (IS_DES(flags))
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-		cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
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-
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-	if (IS_3DES(flags))
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-		cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
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-
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-	switch (flags & QCE_MODE_MASK) {
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-	case QCE_MODE_ECB:
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-		cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
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-		break;
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-	case QCE_MODE_CBC:
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-		cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
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-		break;
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-	case QCE_MODE_CTR:
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-		cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
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-		break;
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-	case QCE_MODE_XTS:
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-		cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
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-		break;
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-	case QCE_MODE_CCM:
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-		cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
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-		cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
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-		break;
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-	default:
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-		return ~0;
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-	}
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-
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-	return cfg;
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+	return config;
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 }
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63
 
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+void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
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+{
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+	__be32 *d = dst;
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+	const u8 *s = src;
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+	unsigned int n;
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+
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+	n = len / sizeof(u32);
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+	for (; n > 0; n--) {
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+		*d = cpu_to_be32p((const __u32 *) s);
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+		s += sizeof(__u32);
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+		d++;
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+	}
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+}
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+
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+static void qce_setup_config(struct qce_device *qce)
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+{
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+	u32 config;
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+
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+	/* get big endianness */
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+	config = qce_config_reg(qce, 0);
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+
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+	/* clear status */
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+	qce_write(qce, REG_STATUS, 0);
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+	qce_write(qce, REG_CONFIG, config);
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+}
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+
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+static inline void qce_crypto_go(struct qce_device *qce)
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+{
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+	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
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+}
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+
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+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
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 static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
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 {
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 	u32 cfg = 0;
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@@ -143,88 +137,6 @@
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 		cfg |= BIT(AUTH_LAST_SHIFT) | BIT(AUTH_FIRST_SHIFT);
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138
 
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 	return cfg;
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-}
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-
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-static u32 qce_config_reg(struct qce_device *qce, int little)
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-{
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-	u32 beats = (qce->burst_size >> 3) - 1;
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-	u32 pipe_pair = qce->pipe_pair_id;
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-	u32 config;
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-
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-	config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
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-	config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
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-		  BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
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-	config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
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-	config &= ~HIGH_SPD_EN_N_SHIFT;
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-
160
-	if (little)
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-		config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
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-
163
-	return config;
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-}
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-
166
-void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
167
-{
168
-	__be32 *d = dst;
169
-	const u8 *s = src;
170
-	unsigned int n;
171
-
172
-	n = len / sizeof(u32);
173
-	for (; n > 0; n--) {
174
-		*d = cpu_to_be32p((const __u32 *) s);
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-		s += sizeof(__u32);
176
-		d++;
177
-	}
178
-}
179
-
180
-static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
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-{
182
-	u8 swap[QCE_AES_IV_LENGTH];
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-	u32 i, j;
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-
185
-	if (ivsize > QCE_AES_IV_LENGTH)
186
-		return;
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-
188
-	memset(swap, 0, QCE_AES_IV_LENGTH);
189
-
190
-	for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
191
-	     i < QCE_AES_IV_LENGTH; i++, j--)
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-		swap[i] = src[j];
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-
194
-	qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
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-}
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-
197
-static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
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-		       unsigned int enckeylen, unsigned int cryptlen)
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-{
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-	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
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-	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
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-	unsigned int xtsdusize;
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-
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-	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
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-			       enckeylen / 2);
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-	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
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-
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-	/* xts du size 512B */
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-	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
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-	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
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-}
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-
213
-static void qce_setup_config(struct qce_device *qce)
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-{
215
-	u32 config;
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-
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-	/* get big endianness */
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-	config = qce_config_reg(qce, 0);
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-
220
-	/* clear status */
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-	qce_write(qce, REG_STATUS, 0);
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-	qce_write(qce, REG_CONFIG, config);
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-}
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-
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-static inline void qce_crypto_go(struct qce_device *qce)
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-{
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-	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
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140
 }
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141
 
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 static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
..
..
@@ -311,14 +223,95 @@
311
223
 
312
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 	return 0;
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 }
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+#endif
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227
 
315
-static int qce_setup_regs_ablkcipher(struct crypto_async_request *async_req,
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+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
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+static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
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+{
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+	u32 cfg = 0;
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+
233
+	if (IS_AES(flags)) {
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+		if (aes_key_size == AES_KEYSIZE_128)
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+			cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
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+		else if (aes_key_size == AES_KEYSIZE_256)
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+			cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
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+	}
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+
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+	if (IS_AES(flags))
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+		cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
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+	else if (IS_DES(flags) || IS_3DES(flags))
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+		cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
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+
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+	if (IS_DES(flags))
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+		cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
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+
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+	if (IS_3DES(flags))
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+		cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
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+
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+	switch (flags & QCE_MODE_MASK) {
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+	case QCE_MODE_ECB:
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+		cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
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+		break;
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+	case QCE_MODE_CBC:
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+		cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
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+		break;
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+	case QCE_MODE_CTR:
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+		cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
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+		break;
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+	case QCE_MODE_XTS:
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+		cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
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+		break;
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+	case QCE_MODE_CCM:
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+		cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
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+		cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
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+		break;
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+	default:
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+		return ~0;
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+	}
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+
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+	return cfg;
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+}
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+
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+static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
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+{
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+	u8 swap[QCE_AES_IV_LENGTH];
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+	u32 i, j;
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+
280
+	if (ivsize > QCE_AES_IV_LENGTH)
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+		return;
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+
283
+	memset(swap, 0, QCE_AES_IV_LENGTH);
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+
285
+	for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
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+	     i < QCE_AES_IV_LENGTH; i++, j--)
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+		swap[i] = src[j];
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+
289
+	qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
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+}
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+
292
+static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
293
+		       unsigned int enckeylen, unsigned int cryptlen)
294
+{
295
+	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
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+	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
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+	unsigned int xtsdusize;
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+
299
+	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
300
+			       enckeylen / 2);
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+	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
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+
303
+	/* xts du size 512B */
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+	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
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+	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
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+}
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+
308
+static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
316
309
 				     u32 totallen, u32 offset)
317
310
 {
318
-	struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
319
-	struct qce_cipher_reqctx *rctx = ablkcipher_request_ctx(req);
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+	struct skcipher_request *req = skcipher_request_cast(async_req);
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+	struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
320
313
 	struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
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-	struct qce_alg_template *tmpl = to_cipher_tmpl(async_req->tfm);
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+	struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req));
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315
 	struct qce_device *qce = tmpl->qce;
323
316
 	__be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0};
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317
 	__be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0};
..
..
@@ -392,15 +385,20 @@
392
385
 
393
386
 	return 0;
394
387
 }
388
+#endif
395
389
 
396
390
 int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
397
391
 	      u32 offset)
398
392
 {
399
393
 	switch (type) {
400
-	case CRYPTO_ALG_TYPE_ABLKCIPHER:
401
-		return qce_setup_regs_ablkcipher(async_req, totallen, offset);
394
+#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
395
+	case CRYPTO_ALG_TYPE_SKCIPHER:
396
+		return qce_setup_regs_skcipher(async_req, totallen, offset);
397
+#endif
398
+#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
402
399
 	case CRYPTO_ALG_TYPE_AHASH:
403
400
 		return qce_setup_regs_ahash(async_req, totallen, offset);
401
+#endif
404
402
 	default:
405
403
 		return -EINVAL;
406
404
 	}