change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/crypto/cavium/nitrox/nitrox_main.c
..
..
@@ -1,6 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 #include <linux/aer.h>
2
3
 #include <linux/delay.h>
3
-#include <linux/debugfs.h>
4
4
 #include <linux/firmware.h>
5
5
 #include <linux/list.h>
6
6
 #include <linux/module.h>
..
..
@@ -11,16 +11,23 @@
11
11
 #include "nitrox_dev.h"
12
12
 #include "nitrox_common.h"
13
13
 #include "nitrox_csr.h"
14
+#include "nitrox_hal.h"
15
+#include "nitrox_isr.h"
16
+#include "nitrox_debugfs.h"
14
17
 
15
18
 #define CNN55XX_DEV_ID	0x12
16
-#define MAX_PF_QUEUES	64
17
19
 #define UCODE_HLEN 48
18
-#define SE_GROUP 0
20
+#define DEFAULT_SE_GROUP 0
21
+#define DEFAULT_AE_GROUP 0
19
22
 
20
-#define DRIVER_VERSION "1.0"
23
+#define DRIVER_VERSION "1.2"
24
+#define CNN55XX_UCD_BLOCK_SIZE 32768
25
+#define CNN55XX_MAX_UCODE_SIZE (CNN55XX_UCD_BLOCK_SIZE * 2)
21
26
 #define FW_DIR "cavium/"
22
27
 /* SE microcode */
23
28
 #define SE_FW	FW_DIR "cnn55xx_se.fw"
29
+/* AE microcode */
30
+#define AE_FW	FW_DIR "cnn55xx_ae.fw"
24
31
 
25
32
 static const char nitrox_driver_name[] = "CNN55XX";
26
33
 
..
..
@@ -42,6 +49,15 @@
42
49
 module_param(qlen, uint, 0644);
43
50
 MODULE_PARM_DESC(qlen, "Command queue length - default 2048");
44
51
 
52
+#ifdef CONFIG_PCI_IOV
53
+int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs);
54
+#else
55
+int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs)
56
+{
57
+	return 0;
58
+}
59
+#endif
60
+
45
61
 /**
46
62
  * struct ucode - Firmware Header
47
63
  * @id: microcode ID
..
..
@@ -55,16 +71,16 @@
55
71
 	char version[VERSION_LEN - 1];
56
72
 	__be32 code_size;
57
73
 	u8 raz[12];
58
-	u64 code[0];
74
+	u64 code[];
59
75
 };
60
76
 
61
77
 /**
62
78
  * write_to_ucd_unit - Write Firmware to NITROX UCD unit
63
79
  */
64
-static void write_to_ucd_unit(struct nitrox_device *ndev,
65
-			      struct ucode *ucode)
80
+static void write_to_ucd_unit(struct nitrox_device *ndev, u32 ucode_size,
81
+			      u64 *ucode_data, int block_num)
66
82
 {
67
-	u32 code_size = be32_to_cpu(ucode->code_size) * 2;
83
+	u32 code_size;
68
84
 	u64 offset, data;
69
85
 	int i = 0;
70
86
 
..
..
@@ -85,11 +101,11 @@
85
101
 
86
102
 	/* set the block number */
87
103
 	offset = UCD_UCODE_LOAD_BLOCK_NUM;
88
-	nitrox_write_csr(ndev, offset, 0);
104
+	nitrox_write_csr(ndev, offset, block_num);
89
105
 
90
-	code_size = roundup(code_size, 8);
106
+	code_size = roundup(ucode_size, 16);
91
107
 	while (code_size) {
92
-		data = ucode->code[i];
108
+		data = ucode_data[i];
93
109
 		/* write 8 bytes at a time */
94
110
 		offset = UCD_UCODE_LOAD_IDX_DATAX(i);
95
111
 		nitrox_write_csr(ndev, offset, data);
..
..
@@ -97,29 +113,23 @@
97
113
 		i++;
98
114
 	}
99
115
 
100
-	/* put all SE cores in group 0 */
101
-	offset = POM_GRP_EXECMASKX(SE_GROUP);
102
-	nitrox_write_csr(ndev, offset, (~0ULL));
103
-
104
-	for (i = 0; i < ndev->hw.se_cores; i++) {
105
-		/*
106
-		 * write block number and firware length
107
-		 * bit:<2:0> block number
108
-		 * bit:3 is set SE uses 32KB microcode
109
-		 * bit:3 is clear SE uses 64KB microcode
110
-		 */
111
-		offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
112
-		nitrox_write_csr(ndev, offset, 0x8);
113
-	}
114
116
 	usleep_range(300, 400);
115
117
 }
116
118
 
117
-static int nitrox_load_fw(struct nitrox_device *ndev, const char *fw_name)
119
+static int nitrox_load_fw(struct nitrox_device *ndev)
118
120
 {
119
121
 	const struct firmware *fw;
122
+	const char *fw_name;
120
123
 	struct ucode *ucode;
121
-	int ret;
124
+	u64 *ucode_data;
125
+	u64 offset;
126
+	union ucd_core_eid_ucode_block_num core_2_eid_val;
127
+	union aqm_grp_execmsk_lo aqm_grp_execmask_lo;
128
+	union aqm_grp_execmsk_hi aqm_grp_execmask_hi;
129
+	u32 ucode_size;
130
+	int ret, i = 0;
122
131
 
132
+	fw_name = SE_FW;
123
133
 	dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
124
134
 
125
135
 	ret = request_firmware(&fw, fw_name, DEV(ndev));
..
..
@@ -129,16 +139,101 @@
129
139
 	}
130
140
 
131
141
 	ucode = (struct ucode *)fw->data;
132
-	/* copy the firmware version */
133
-	memcpy(ndev->hw.fw_name, ucode->version, (VERSION_LEN - 2));
134
-	ndev->hw.fw_name[VERSION_LEN - 1] = '\0';
135
142
 
136
-	write_to_ucd_unit(ndev, ucode);
143
+	ucode_size = be32_to_cpu(ucode->code_size) * 2;
144
+	if (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {
145
+		dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n",
146
+			ucode_size, fw_name);
147
+		release_firmware(fw);
148
+		return -EINVAL;
149
+	}
150
+	ucode_data = ucode->code;
151
+
152
+	/* copy the firmware version */
153
+	memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2));
154
+	ndev->hw.fw_name[0][VERSION_LEN - 1] = '\0';
155
+
156
+	/* Load SE Firmware on UCD Block 0 */
157
+	write_to_ucd_unit(ndev, ucode_size, ucode_data, 0);
158
+
137
159
 	release_firmware(fw);
138
160
 
139
-	set_bit(NITROX_UCODE_LOADED, &ndev->status);
140
-	/* barrier to sync with other cpus */
141
-	smp_mb__after_atomic();
161
+	/* put all SE cores in DEFAULT_SE_GROUP */
162
+	offset = POM_GRP_EXECMASKX(DEFAULT_SE_GROUP);
163
+	nitrox_write_csr(ndev, offset, (~0ULL));
164
+
165
+	/* write block number and firmware length
166
+	 * bit:<2:0> block number
167
+	 * bit:3 is set SE uses 32KB microcode
168
+	 * bit:3 is clear SE uses 64KB microcode
169
+	 */
170
+	core_2_eid_val.value = 0ULL;
171
+	core_2_eid_val.ucode_blk = 0;
172
+	if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
173
+		core_2_eid_val.ucode_len = 1;
174
+	else
175
+		core_2_eid_val.ucode_len = 0;
176
+
177
+	for (i = 0; i < ndev->hw.se_cores; i++) {
178
+		offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
179
+		nitrox_write_csr(ndev, offset, core_2_eid_val.value);
180
+	}
181
+
182
+
183
+	fw_name = AE_FW;
184
+	dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
185
+
186
+	ret = request_firmware(&fw, fw_name, DEV(ndev));
187
+	if (ret < 0) {
188
+		dev_err(DEV(ndev), "failed to get firmware %s\n", fw_name);
189
+		return ret;
190
+	}
191
+
192
+	ucode = (struct ucode *)fw->data;
193
+
194
+	ucode_size = be32_to_cpu(ucode->code_size) * 2;
195
+	if (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {
196
+		dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n",
197
+			ucode_size, fw_name);
198
+		release_firmware(fw);
199
+		return -EINVAL;
200
+	}
201
+	ucode_data = ucode->code;
202
+
203
+	/* copy the firmware version */
204
+	memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2));
205
+	ndev->hw.fw_name[1][VERSION_LEN - 1] = '\0';
206
+
207
+	/* Load AE Firmware on UCD Block 2 */
208
+	write_to_ucd_unit(ndev, ucode_size, ucode_data, 2);
209
+
210
+	release_firmware(fw);
211
+
212
+	/* put all AE cores in DEFAULT_AE_GROUP */
213
+	offset = AQM_GRP_EXECMSK_LOX(DEFAULT_AE_GROUP);
214
+	aqm_grp_execmask_lo.exec_0_to_39 = 0xFFFFFFFFFFULL;
215
+	nitrox_write_csr(ndev, offset, aqm_grp_execmask_lo.value);
216
+	offset = AQM_GRP_EXECMSK_HIX(DEFAULT_AE_GROUP);
217
+	aqm_grp_execmask_hi.exec_40_to_79 = 0xFFFFFFFFFFULL;
218
+	nitrox_write_csr(ndev, offset, aqm_grp_execmask_hi.value);
219
+
220
+	/* write block number and firmware length
221
+	 * bit:<2:0> block number
222
+	 * bit:3 is set AE uses 32KB microcode
223
+	 * bit:3 is clear AE uses 64KB microcode
224
+	 */
225
+	core_2_eid_val.value = 0ULL;
226
+	core_2_eid_val.ucode_blk = 2;
227
+	if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
228
+		core_2_eid_val.ucode_len = 1;
229
+	else
230
+		core_2_eid_val.ucode_len = 0;
231
+
232
+	for (i = 0; i < ndev->hw.ae_cores; i++) {
233
+		offset = UCD_AE_EID_UCODE_BLOCK_NUMX(i);
234
+		nitrox_write_csr(ndev, offset, core_2_eid_val.value);
235
+	}
236
+
142
237
 	return 0;
143
238
 }
144
239
 
..
..
@@ -210,7 +305,7 @@
210
305
 	smp_mb__after_atomic();
211
306
 }
212
307
 
213
-static int nitrox_reset_device(struct pci_dev *pdev)
308
+static int nitrox_device_flr(struct pci_dev *pdev)
214
309
 {
215
310
 	int pos = 0;
216
311
 
..
..
@@ -220,15 +315,10 @@
220
315
 		return -ENOMEM;
221
316
 	}
222
317
 
223
-	pos = pci_pcie_cap(pdev);
224
-	if (!pos)
225
-		return -ENOTTY;
318
+	/* check flr support */
319
+	if (pcie_has_flr(pdev))
320
+		pcie_flr(pdev);
226
321
 
227
-	if (!pci_wait_for_pending_transaction(pdev))
228
-		dev_err(&pdev->dev, "waiting for pending transaction\n");
229
-
230
-	pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
231
-	msleep(100);
232
322
 	pci_restore_state(pdev);
233
323
 
234
324
 	return 0;
..
..
@@ -242,7 +332,7 @@
242
332
 	if (err)
243
333
 		return err;
244
334
 
245
-	err = nitrox_pf_init_isr(ndev);
335
+	err = nitrox_register_interrupts(ndev);
246
336
 	if (err)
247
337
 		nitrox_common_sw_cleanup(ndev);
248
338
 
..
..
@@ -251,12 +341,12 @@
251
341
 
252
342
 static void nitrox_pf_sw_cleanup(struct nitrox_device *ndev)
253
343
 {
254
-	nitrox_pf_cleanup_isr(ndev);
344
+	nitrox_unregister_interrupts(ndev);
255
345
 	nitrox_common_sw_cleanup(ndev);
256
346
 }
257
347
 
258
348
 /**
259
- * nitrox_bist_check - Check NITORX BIST registers status
349
+ * nitrox_bist_check - Check NITROX BIST registers status
260
350
  * @ndev: NITROX device
261
351
  */
262
352
 static int nitrox_bist_check(struct nitrox_device *ndev)
..
..
@@ -284,26 +374,6 @@
284
374
 	return 0;
285
375
 }
286
376
 
287
-static void nitrox_get_hwinfo(struct nitrox_device *ndev)
288
-{
289
-	union emu_fuse_map emu_fuse;
290
-	u64 offset;
291
-	int i;
292
-
293
-	for (i = 0; i < NR_CLUSTERS; i++) {
294
-		u8 dead_cores;
295
-
296
-		offset = EMU_FUSE_MAPX(i);
297
-		emu_fuse.value = nitrox_read_csr(ndev, offset);
298
-		if (emu_fuse.s.valid) {
299
-			dead_cores = hweight32(emu_fuse.s.ae_fuse);
300
-			ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
301
-			dead_cores = hweight16(emu_fuse.s.se_fuse);
302
-			ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
303
-		}
304
-	}
305
-}
306
-
307
377
 static int nitrox_pf_hw_init(struct nitrox_device *ndev)
308
378
 {
309
379
 	int err;
..
..
@@ -316,7 +386,9 @@
316
386
 	/* get cores information */
317
387
 	nitrox_get_hwinfo(ndev);
318
388
 
319
-	nitrox_config_nps_unit(ndev);
389
+	nitrox_config_nps_core_unit(ndev);
390
+	nitrox_config_aqm_unit(ndev);
391
+	nitrox_config_nps_pkt_unit(ndev);
320
392
 	nitrox_config_pom_unit(ndev);
321
393
 	nitrox_config_efl_unit(ndev);
322
394
 	/* configure IO units */
..
..
@@ -326,8 +398,8 @@
326
398
 	nitrox_config_lbc_unit(ndev);
327
399
 	nitrox_config_rand_unit(ndev);
328
400
 
329
-	/* load firmware on SE cores */
330
-	err = nitrox_load_fw(ndev, SE_FW);
401
+	/* load firmware on cores */
402
+	err = nitrox_load_fw(ndev);
331
403
 	if (err)
332
404
 		return err;
333
405
 
..
..
@@ -335,135 +407,6 @@
335
407
 
336
408
 	return 0;
337
409
 }
338
-
339
-#if IS_ENABLED(CONFIG_DEBUG_FS)
340
-static int registers_show(struct seq_file *s, void *v)
341
-{
342
-	struct nitrox_device *ndev = s->private;
343
-	u64 offset;
344
-
345
-	/* NPS DMA stats */
346
-	offset = NPS_STATS_PKT_DMA_RD_CNT;
347
-	seq_printf(s, "NPS_STATS_PKT_DMA_RD_CNT  0x%016llx\n",
348
-		   nitrox_read_csr(ndev, offset));
349
-	offset = NPS_STATS_PKT_DMA_WR_CNT;
350
-	seq_printf(s, "NPS_STATS_PKT_DMA_WR_CNT  0x%016llx\n",
351
-		   nitrox_read_csr(ndev, offset));
352
-
353
-	/* BMI/BMO stats */
354
-	offset = BMI_NPS_PKT_CNT;
355
-	seq_printf(s, "BMI_NPS_PKT_CNT  0x%016llx\n",
356
-		   nitrox_read_csr(ndev, offset));
357
-	offset = BMO_NPS_SLC_PKT_CNT;
358
-	seq_printf(s, "BMO_NPS_PKT_CNT  0x%016llx\n",
359
-		   nitrox_read_csr(ndev, offset));
360
-
361
-	return 0;
362
-}
363
-
364
-static int registers_open(struct inode *inode, struct file *file)
365
-{
366
-	return single_open(file, registers_show, inode->i_private);
367
-}
368
-
369
-static const struct file_operations register_fops = {
370
-	.owner = THIS_MODULE,
371
-	.open = registers_open,
372
-	.read = seq_read,
373
-	.llseek = seq_lseek,
374
-	.release = single_release,
375
-};
376
-
377
-static int firmware_show(struct seq_file *s, void *v)
378
-{
379
-	struct nitrox_device *ndev = s->private;
380
-
381
-	seq_printf(s, "Version: %s\n", ndev->hw.fw_name);
382
-	return 0;
383
-}
384
-
385
-static int firmware_open(struct inode *inode, struct file *file)
386
-{
387
-	return single_open(file, firmware_show, inode->i_private);
388
-}
389
-
390
-static const struct file_operations firmware_fops = {
391
-	.owner = THIS_MODULE,
392
-	.open = firmware_open,
393
-	.read = seq_read,
394
-	.llseek = seq_lseek,
395
-	.release = single_release,
396
-};
397
-
398
-static int nitrox_show(struct seq_file *s, void *v)
399
-{
400
-	struct nitrox_device *ndev = s->private;
401
-
402
-	seq_printf(s, "NITROX-5 [idx: %d]\n", ndev->idx);
403
-	seq_printf(s, "  Revision ID: 0x%0x\n", ndev->hw.revision_id);
404
-	seq_printf(s, "  Cores [AE: %u  SE: %u]\n",
405
-		   ndev->hw.ae_cores, ndev->hw.se_cores);
406
-	seq_printf(s, "  Number of Queues: %u\n", ndev->nr_queues);
407
-	seq_printf(s, "  Queue length: %u\n", ndev->qlen);
408
-	seq_printf(s, "  Node: %u\n", ndev->node);
409
-
410
-	return 0;
411
-}
412
-
413
-static int nitrox_open(struct inode *inode, struct file *file)
414
-{
415
-	return single_open(file, nitrox_show, inode->i_private);
416
-}
417
-
418
-static const struct file_operations nitrox_fops = {
419
-	.owner = THIS_MODULE,
420
-	.open = nitrox_open,
421
-	.read = seq_read,
422
-	.llseek = seq_lseek,
423
-	.release = single_release,
424
-};
425
-
426
-static void nitrox_debugfs_exit(struct nitrox_device *ndev)
427
-{
428
-	debugfs_remove_recursive(ndev->debugfs_dir);
429
-	ndev->debugfs_dir = NULL;
430
-}
431
-
432
-static int nitrox_debugfs_init(struct nitrox_device *ndev)
433
-{
434
-	struct dentry *dir, *f;
435
-
436
-	dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
437
-	if (!dir)
438
-		return -ENOMEM;
439
-
440
-	ndev->debugfs_dir = dir;
441
-	f = debugfs_create_file("counters", 0400, dir, ndev, &register_fops);
442
-	if (!f)
443
-		goto err;
444
-	f = debugfs_create_file("firmware", 0400, dir, ndev, &firmware_fops);
445
-	if (!f)
446
-		goto err;
447
-	f = debugfs_create_file("nitrox", 0400, dir, ndev, &nitrox_fops);
448
-	if (!f)
449
-		goto err;
450
-
451
-	return 0;
452
-
453
-err:
454
-	nitrox_debugfs_exit(ndev);
455
-	return -ENODEV;
456
-}
457
-#else
458
-static int nitrox_debugfs_init(struct nitrox_device *ndev)
459
-{
460
-	return 0;
461
-}
462
-
463
-static void nitrox_debugfs_exit(struct nitrox_device *ndev)
464
-{
465
-}
466
-#endif
467
410
 
468
411
 /**
469
412
  * nitrox_probe - NITROX Initialization function.
..
..
@@ -487,7 +430,7 @@
487
430
 		return err;
488
431
 
489
432
 	/* do FLR */
490
-	err = nitrox_reset_device(pdev);
433
+	err = nitrox_device_flr(pdev);
491
434
 	if (err) {
492
435
 		dev_err(&pdev->dev, "FLR failed\n");
493
436
 		pci_disable_device(pdev);
..
..
@@ -551,11 +494,14 @@
551
494
 	if (err)
552
495
 		goto pf_hw_fail;
553
496
 
554
-	err = nitrox_debugfs_init(ndev);
555
-	if (err)
556
-		goto pf_hw_fail;
497
+	nitrox_debugfs_init(ndev);
557
498
 
558
-	set_bit(NITROX_READY, &ndev->status);
499
+	/* clear the statistics */
500
+	atomic64_set(&ndev->stats.posted, 0);
501
+	atomic64_set(&ndev->stats.completed, 0);
502
+	atomic64_set(&ndev->stats.dropped, 0);
503
+
504
+	atomic_set(&ndev->state, __NDEV_READY);
559
505
 	/* barrier to sync with other cpus */
560
506
 	smp_mb__after_atomic();
561
507
 
..
..
@@ -567,7 +513,7 @@
567
513
 
568
514
 crypto_fail:
569
515
 	nitrox_debugfs_exit(ndev);
570
-	clear_bit(NITROX_READY, &ndev->status);
516
+	atomic_set(&ndev->state, __NDEV_NOT_READY);
571
517
 	/* barrier to sync with other cpus */
572
518
 	smp_mb__after_atomic();
573
519
 pf_hw_fail:
..
..
@@ -602,11 +548,16 @@
602
548
 	dev_info(DEV(ndev), "Removing Device %x:%x\n",
603
549
 		 ndev->hw.vendor_id, ndev->hw.device_id);
604
550
 
605
-	clear_bit(NITROX_READY, &ndev->status);
551
+	atomic_set(&ndev->state, __NDEV_NOT_READY);
606
552
 	/* barrier to sync with other cpus */
607
553
 	smp_mb__after_atomic();
608
554
 
609
555
 	nitrox_remove_from_devlist(ndev);
556
+
557
+#ifdef CONFIG_PCI_IOV
558
+	/* disable SR-IOV */
559
+	nitrox_sriov_configure(pdev, 0);
560
+#endif
610
561
 	nitrox_crypto_unregister();
611
562
 	nitrox_debugfs_exit(ndev);
612
563
 	nitrox_pf_sw_cleanup(ndev);
..
..
@@ -632,6 +583,9 @@
632
583
 	.probe = nitrox_probe,
633
584
 	.remove	= nitrox_remove,
634
585
 	.shutdown = nitrox_shutdown,
586
+#ifdef CONFIG_PCI_IOV
587
+	.sriov_configure = nitrox_sriov_configure,
588
+#endif
635
589
 };
636
590
 
637
591
 module_pci_driver(nitrox_driver);