change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/clk/socfpga/clk-gate-s10.c
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@@ -3,6 +3,7 @@
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  * Copyright (C) 2017, Intel Corporation
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  */
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 #include <linux/clk-provider.h>
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+#include <linux/io.h>
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 #include <linux/slab.h>
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 #include "stratix10-clk.h"
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 #include "clk.h"
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@@ -64,55 +65,51 @@
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 	.get_parent = socfpga_gate_get_parent,
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 };
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-struct clk *s10_register_gate(const char *name, const char *parent_name,
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-			      const char * const *parent_names,
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-			      u8 num_parents, unsigned long flags,
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-			      void __iomem *regbase, unsigned long gate_reg,
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-			      unsigned long gate_idx, unsigned long div_reg,
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-			      unsigned long div_offset, u8 div_width,
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-			      unsigned long bypass_reg, u8 bypass_shift,
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-			      u8 fixed_div)
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+struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
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 {
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 	struct clk *clk;
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 	struct socfpga_gate_clk *socfpga_clk;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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+	const char *parent_name = clks->parent_name;
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 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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 	if (!socfpga_clk)
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 		return NULL;
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-	socfpga_clk->hw.reg = regbase + gate_reg;
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-	socfpga_clk->hw.bit_idx = gate_idx;
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+	socfpga_clk->hw.reg = regbase + clks->gate_reg;
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+	socfpga_clk->hw.bit_idx = clks->gate_idx;
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 	gateclk_ops.enable = clk_gate_ops.enable;
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 	gateclk_ops.disable = clk_gate_ops.disable;
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-	socfpga_clk->fixed_div = fixed_div;
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+	socfpga_clk->fixed_div = clks->fixed_div;
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-	if (div_reg)
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-		socfpga_clk->div_reg = regbase + div_reg;
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+	if (clks->div_reg)
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+		socfpga_clk->div_reg = regbase + clks->div_reg;
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 	else
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 		socfpga_clk->div_reg = NULL;
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-	socfpga_clk->width = div_width;
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-	socfpga_clk->shift = div_offset;
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+	socfpga_clk->width = clks->div_width;
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+	socfpga_clk->shift = clks->div_offset;
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-	if (bypass_reg)
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-		socfpga_clk->bypass_reg = regbase + bypass_reg;
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+	if (clks->bypass_reg)
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+		socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
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 	else
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 		socfpga_clk->bypass_reg = NULL;
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-	socfpga_clk->bypass_shift = bypass_shift;
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+	socfpga_clk->bypass_shift = clks->bypass_shift;
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-	if (streq(name, "cs_pdbg_clk"))
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+	if (streq(clks->name, "cs_pdbg_clk"))
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 		init.ops = &dbgclk_ops;
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 	else
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 		init.ops = &gateclk_ops;
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-	init.name = name;
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-	init.flags = flags;
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+	init.name = clks->name;
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+	init.flags = clks->flags;
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-	init.num_parents = num_parents;
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-	init.parent_names = parent_names ? parent_names : &parent_name;
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+	init.num_parents = clks->num_parents;
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+	init.parent_names = parent_name ? &parent_name : NULL;
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+	if (init.parent_names == NULL)
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+		init.parent_data = clks->parent_data;
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 	socfpga_clk->hw.hw.init = &init;
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 	clk = clk_register(NULL, &socfpga_clk->hw.hw);
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@@ -120,6 +117,5 @@
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 		kfree(socfpga_clk);
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 		return NULL;
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 	}
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-
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 	return clk;
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 }