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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/clk/renesas/r8a77970-cpg-mssr.c
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@@ -1,17 +1,15 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
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  *
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- * Copyright (C) 2017 Cogent Embedded Inc.
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+ * Copyright (C) 2017-2018 Cogent Embedded Inc.
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  *
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  * Based on r8a7795-cpg-mssr.c
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  *
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  * Copyright (C) 2015 Glider bvba
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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  */
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11
 
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+#include <linux/clk-provider.h>
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 #include <linux/device.h>
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 #include <linux/init.h>
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 #include <linux/kernel.h>
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@@ -21,6 +19,13 @@
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19
 
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 #include "renesas-cpg-mssr.h"
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 #include "rcar-gen3-cpg.h"
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+
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+#define CPG_SD0CKCR		0x0074
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+
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+enum r8a77970_clk_types {
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+	CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
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+	CLK_TYPE_R8A77970_SD0,
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+};
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29
 
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 enum clk_ids {
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 	/* Core Clock Outputs exported to DT */
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@@ -40,6 +45,20 @@
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45
 
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 	/* Module Clocks */
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 	MOD_CLK_BASE
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+};
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+
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+static spinlock_t cpg_lock;
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+
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+static const struct clk_div_table cpg_sd0h_div_table[] = {
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+	{  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
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+	{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
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+	{  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
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+};
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+
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+static const struct clk_div_table cpg_sd0_div_table[] = {
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+	{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
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+	{  8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
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+	{  0,  0 },
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 };
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63
 
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 static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
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@@ -68,8 +87,16 @@
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 	DEF_FIXED("s2d2",	R8A77970_CLK_S2D2,  CLK_PLL1_DIV2, 12, 1),
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 	DEF_FIXED("s2d4",	R8A77970_CLK_S2D4,  CLK_PLL1_DIV2, 24, 1),
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+	DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
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+		 CLK_PLL1_DIV2),
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+	DEF_BASE("sd0",	R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
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+
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+	DEF_FIXED("rpc",	R8A77970_CLK_RPC,   CLK_PLL1_DIV2,  5, 1),
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+	DEF_FIXED("rpcd2",	R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
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+
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 	DEF_FIXED("cl",		R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
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 	DEF_FIXED("cp",		R8A77970_CLK_CP,    CLK_EXTAL,	    2, 1),
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+	DEF_FIXED("cpex",	R8A77970_CLK_CPEX,  CLK_EXTAL,	    2, 1),
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 	DEF_DIV6P1("canfd",	R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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 	DEF_DIV6P1("mso",	R8A77970_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
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@@ -80,6 +107,11 @@
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 };
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 static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
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+	DEF_MOD("tmu4",			 121,	R8A77970_CLK_S2D2),
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+	DEF_MOD("tmu3",			 122,	R8A77970_CLK_S2D2),
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+	DEF_MOD("tmu2",			 123,	R8A77970_CLK_S2D2),
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+	DEF_MOD("tmu1",			 124,	R8A77970_CLK_S2D2),
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+	DEF_MOD("tmu0",			 125,	R8A77970_CLK_CP),
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 	DEF_MOD("ivcp1e",		 127,	R8A77970_CLK_S2D1),
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 	DEF_MOD("scif4",		 203,	R8A77970_CLK_S2D4),
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 	DEF_MOD("scif3",		 204,	R8A77970_CLK_S2D4),
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@@ -92,6 +124,12 @@
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 	DEF_MOD("mfis",			 213,	R8A77970_CLK_S2D2),
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 	DEF_MOD("sys-dmac2",		 217,	R8A77970_CLK_S2D1),
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 	DEF_MOD("sys-dmac1",		 218,	R8A77970_CLK_S2D1),
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+	DEF_MOD("cmt3",			 300,	R8A77970_CLK_R),
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+	DEF_MOD("cmt2",			 301,	R8A77970_CLK_R),
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+	DEF_MOD("cmt1",			 302,	R8A77970_CLK_R),
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+	DEF_MOD("cmt0",			 303,	R8A77970_CLK_R),
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+	DEF_MOD("tpu0",			 304,	R8A77970_CLK_S2D4),
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+	DEF_MOD("sd-if",		 314,	R8A77970_CLK_SD0),
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 	DEF_MOD("rwdt",			 402,	R8A77970_CLK_R),
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 	DEF_MOD("intc-ex",		 407,	R8A77970_CLK_CP),
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 	DEF_MOD("intc-ap",		 408,	R8A77970_CLK_S2D1),
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@@ -118,6 +156,7 @@
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 	DEF_MOD("gpio1",		 911,	R8A77970_CLK_CP),
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 	DEF_MOD("gpio0",		 912,	R8A77970_CLK_CP),
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 	DEF_MOD("can-fd",		 914,	R8A77970_CLK_S2D2),
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+	DEF_MOD("rpc-if",		 917,	R8A77970_CLK_RPC),
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 	DEF_MOD("i2c4",			 927,	R8A77970_CLK_S2D2),
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 	DEF_MOD("i2c3",			 928,	R8A77970_CLK_S2D2),
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 	DEF_MOD("i2c2",			 929,	R8A77970_CLK_S2D2),
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@@ -126,9 +165,9 @@
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 };
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 static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
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+	MOD_CLK_ID(402),	/* RWDT */
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 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
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 };
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-
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 /*
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  * CPG Clock Data
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@@ -173,9 +212,44 @@
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 	if (error)
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 		return error;
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214
 
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+	spin_lock_init(&cpg_lock);
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+
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 	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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 	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
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+}
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+
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+static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
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+	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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+	struct clk **clks, void __iomem *base,
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+	struct raw_notifier_head *notifiers)
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+{
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+	const struct clk_div_table *table;
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+	const struct clk *parent;
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+	unsigned int shift;
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+
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+	switch (core->type) {
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+	case CLK_TYPE_R8A77970_SD0H:
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+		table = cpg_sd0h_div_table;
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+		shift = 8;
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+		break;
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+	case CLK_TYPE_R8A77970_SD0:
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+		table = cpg_sd0_div_table;
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+		shift = 4;
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+		break;
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+	default:
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+		return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
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+						  notifiers);
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+	}
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+
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+	parent = clks[core->parent];
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+	if (IS_ERR(parent))
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+		return ERR_CAST(parent);
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+
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+	return clk_register_divider_table(NULL, core->name,
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+					  __clk_get_name(parent), 0,
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+					  base + CPG_SD0CKCR,
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+					  shift, 4, 0, table, &cpg_lock);
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 }
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 const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
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@@ -196,5 +270,5 @@
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 	/* Callbacks */
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 	.init = r8a77970_cpg_mssr_init,
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-	.cpg_clk_register = rcar_gen3_cpg_clk_register,
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+	.cpg_clk_register = r8a77970_cpg_clk_register,
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 };