change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/clk/renesas/clk-rz.c
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@@ -1,17 +1,15 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * RZ/A1 Core CPG Clocks
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  *
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  * Copyright (C) 2013 Ideas On Board SPRL
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  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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  */
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 #include <linux/clk-provider.h>
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 #include <linux/clk/renesas.h>
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 #include <linux/init.h>
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+#include <linux/io.h>
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 #include <linux/kernel.h>
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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@@ -39,8 +37,8 @@
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 	void __iomem *ppr0, *pibc0;
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 	u16 modes;
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-	ppr0 = ioremap_nocache(PPR0, 2);
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-	pibc0 = ioremap_nocache(PIBC0, 2);
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+	ppr0 = ioremap(PPR0, 2);
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+	pibc0 = ioremap(PIBC0, 2);
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 	BUG_ON(!ppr0 || !pibc0);
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 	iowrite16(4, pibc0);	/* enable input buffer */
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 	modes = ioread16(ppr0);
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@@ -113,8 +111,8 @@
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 		clk = rz_cpg_register_clock(np, cpg, name);
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 		if (IS_ERR(clk))
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-			pr_err("%s: failed to register %s %s clock (%ld)\n",
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-			       __func__, np->name, name, PTR_ERR(clk));
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+			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
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+			       __func__, np, name, PTR_ERR(clk));
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 		else
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 			cpg->data.clks[i] = clk;
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 	}