forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777
kernel/drivers/clk/imx/clk-imx31.c
....@@ -1,18 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version 2
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- * of the License, or (at your option) any later version.
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation.
164 */
175
186 #include <linux/module.h>
....@@ -142,77 +130,6 @@
142130 clk_prepare_enable(clk[iim_gate]);
143131 mx31_revision();
144132 clk_disable_unprepare(clk[iim_gate]);
145
-}
146
-
147
-int __init mx31_clocks_init(unsigned long fref)
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-{
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- void __iomem *base;
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-
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- base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
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- if (!base)
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- panic("%s: failed to map registers\n", __func__);
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-
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- _mx31_clocks_init(base, fref);
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-
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- clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
158
- clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
159
- clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
160
- clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
161
- clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
162
- clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
163
- clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
164
- clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
165
- clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
166
- clk_register_clkdev(clk[epit1_gate], "epit", NULL);
167
- clk_register_clkdev(clk[epit2_gate], "epit", NULL);
168
- clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
169
- clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
170
- clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
171
- clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
172
- clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
173
- clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
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- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
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- clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
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- clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
177
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
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- clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
179
- clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
180
- clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
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- clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
182
- clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
183
- clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
184
- clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
185
- /* i.mx31 has the i.mx21 type uart */
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- clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
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- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
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- clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
189
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
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- clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
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- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
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- clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
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- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
194
- clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
195
- clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
196
- clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
197
- clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
198
- clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
199
- clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
200
- clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
201
- clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
202
- clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
203
- clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
204
- clk_register_clkdev(clk[firi_gate], "firi", NULL);
205
- clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
206
- clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
207
- clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
208
- clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
209
- clk_register_clkdev(clk[iim_gate], "iim", NULL);
210
-
211
-
212
- imx_register_uart_clocks(uart_clks);
213
- mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
214
-
215
- return 0;
216133 }
217134
218135 static void __init mx31_clocks_init_dt(struct device_node *np)