.. | .. |
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3 | 3 | #include <linux/clk-provider.h> |
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4 | 4 | #include <linux/clkdev.h> |
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5 | 5 | #include <linux/err.h> |
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| 6 | +#include <linux/io.h> |
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6 | 7 | #include <linux/of.h> |
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7 | 8 | #include <linux/of_address.h> |
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8 | 9 | #include <dt-bindings/clock/imx27-clock.h> |
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.. | .. |
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47 | 48 | |
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48 | 49 | static struct clk *clk[IMX27_CLK_MAX]; |
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49 | 50 | static struct clk_onecell_data clk_data; |
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50 | | - |
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51 | | -static struct clk ** const uart_clks[] __initconst = { |
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52 | | - &clk[IMX27_CLK_PER1_GATE], |
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53 | | - &clk[IMX27_CLK_UART1_IPG_GATE], |
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54 | | - &clk[IMX27_CLK_UART2_IPG_GATE], |
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55 | | - &clk[IMX27_CLK_UART3_IPG_GATE], |
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56 | | - &clk[IMX27_CLK_UART4_IPG_GATE], |
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57 | | - &clk[IMX27_CLK_UART5_IPG_GATE], |
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58 | | - &clk[IMX27_CLK_UART6_IPG_GATE], |
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59 | | - NULL |
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60 | | -}; |
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61 | 51 | |
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62 | 52 | static void __init _mx27_clocks_init(unsigned long fref) |
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63 | 53 | { |
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.. | .. |
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175 | 165 | |
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176 | 166 | clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); |
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177 | 167 | |
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178 | | - imx_register_uart_clocks(uart_clks); |
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| 168 | + imx_register_uart_clocks(7); |
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179 | 169 | |
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180 | 170 | imx_print_silicon_rev("i.MX27", mx27_revision()); |
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181 | | -} |
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182 | | - |
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183 | | -int __init mx27_clocks_init(unsigned long fref) |
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184 | | -{ |
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185 | | - ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K); |
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186 | | - |
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187 | | - _mx27_clocks_init(fref); |
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188 | | - |
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189 | | - clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); |
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190 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); |
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191 | | - clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); |
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192 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); |
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193 | | - clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); |
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194 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); |
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195 | | - clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); |
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196 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); |
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197 | | - clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); |
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198 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); |
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199 | | - clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); |
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200 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); |
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201 | | - clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); |
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202 | | - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); |
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203 | | - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); |
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204 | | - clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); |
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205 | | - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); |
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206 | | - clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); |
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207 | | - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); |
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208 | | - clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); |
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209 | | - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); |
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210 | | - clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); |
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211 | | - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); |
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212 | | - clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); |
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213 | | - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); |
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214 | | - clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); |
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215 | | - clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); |
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216 | | - clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); |
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217 | | - clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); |
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218 | | - clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); |
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219 | | - clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); |
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220 | | - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); |
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221 | | - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); |
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222 | | - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); |
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223 | | - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); |
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224 | | - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); |
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225 | | - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); |
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226 | | - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); |
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227 | | - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); |
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228 | | - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); |
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229 | | - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); |
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230 | | - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); |
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231 | | - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); |
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232 | | - clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); |
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233 | | - clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); |
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234 | | - clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); |
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235 | | - clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); |
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236 | | - clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); |
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237 | | - clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); |
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238 | | - clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); |
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239 | | - clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); |
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240 | | - clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); |
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241 | | - clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); |
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242 | | - clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); |
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243 | | - clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); |
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244 | | - clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); |
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245 | | - clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); |
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246 | | - clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); |
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247 | | - clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); |
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248 | | - clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); |
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249 | | - clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); |
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250 | | - |
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251 | | - mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21); |
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252 | | - |
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253 | | - return 0; |
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254 | 171 | } |
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255 | 172 | |
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256 | 173 | static void __init mx27_clocks_init_dt(struct device_node *np) |
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