change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/drivers/clk/imx/clk-gate2.c
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@@ -1,15 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Gated clock implementation
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  */
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8
 
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 #include <linux/clk-provider.h>
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+#include <linux/export.h>
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 #include <linux/module.h>
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 #include <linux/slab.h>
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 #include <linux/io.h>
..
..
@@ -18,7 +16,7 @@
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 #include "clk.h"
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17
 
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 /**
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- * DOC: basic gatable clock which can gate and ungate it's ouput
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+ * DOC: basic gateable clock which can gate and ungate its output
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  *
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  * Traits of this clock:
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  * prepare - clk_(un)prepare only ensures parent is (un)prepared
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@@ -43,29 +41,34 @@
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 {
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 	struct clk_gate2 *gate = to_clk_gate2(hw);
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 	u32 reg;
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-	unsigned long flags = 0;
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+	unsigned long flags;
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+	int ret = 0;
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46
 
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 	spin_lock_irqsave(gate->lock, flags);
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 	if (gate->share_count && (*gate->share_count)++ > 0)
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 		goto out;
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-	reg = readl(gate->reg);
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-	reg &= ~(3 << gate->bit_idx);
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-	reg |= gate->cgr_val << gate->bit_idx;
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-	writel(reg, gate->reg);
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+	if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
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+		ret = clk_gate_ops.enable(hw);
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+	} else {
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+		reg = readl(gate->reg);
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+		reg &= ~(3 << gate->bit_idx);
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+		reg |= gate->cgr_val << gate->bit_idx;
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+		writel(reg, gate->reg);
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+	}
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 out:
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 	spin_unlock_irqrestore(gate->lock, flags);
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63
 
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-	return 0;
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+	return ret;
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 }
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 static void clk_gate2_disable(struct clk_hw *hw)
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 {
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 	struct clk_gate2 *gate = to_clk_gate2(hw);
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 	u32 reg;
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-	unsigned long flags = 0;
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+	unsigned long flags;
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 	spin_lock_irqsave(gate->lock, flags);
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..
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@@ -76,9 +79,13 @@
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 			goto out;
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 	}
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-	reg = readl(gate->reg);
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-	reg &= ~(3 << gate->bit_idx);
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-	writel(reg, gate->reg);
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+	if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
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+		clk_gate_ops.disable(hw);
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+	} else {
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+		reg = readl(gate->reg);
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+		reg &= ~(3 << gate->bit_idx);
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+		writel(reg, gate->reg);
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+	}
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 out:
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 	spin_unlock_irqrestore(gate->lock, flags);
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@@ -98,14 +105,20 @@
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 {
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 	struct clk_gate2 *gate = to_clk_gate2(hw);
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+	if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
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+		return clk_gate_ops.is_enabled(hw);
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+
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 	return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
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 }
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 static void clk_gate2_disable_unused(struct clk_hw *hw)
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 {
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 	struct clk_gate2 *gate = to_clk_gate2(hw);
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-	unsigned long flags = 0;
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+	unsigned long flags;
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 	u32 reg;
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+
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+	if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
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+		return;
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 	spin_lock_irqsave(gate->lock, flags);
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@@ -125,15 +138,16 @@
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 	.is_enabled = clk_gate2_is_enabled,
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 };
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-struct clk *clk_register_gate2(struct device *dev, const char *name,
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+struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
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 		const char *parent_name, unsigned long flags,
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 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
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 		u8 clk_gate2_flags, spinlock_t *lock,
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 		unsigned int *share_count)
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 {
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 	struct clk_gate2 *gate;
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-	struct clk *clk;
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-	struct clk_init_data init = {};
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+	struct clk_hw *hw;
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+	struct clk_init_data init;
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+	int ret;
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 	gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
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 	if (!gate)
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@@ -154,10 +168,14 @@
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 	init.num_parents = parent_name ? 1 : 0;
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 	gate->hw.init = &init;
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+	hw = &gate->hw;
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-	clk = clk_register(dev, &gate->hw);
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-	if (IS_ERR(clk))
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+	ret = clk_hw_register(dev, hw);
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+	if (ret) {
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 		kfree(gate);
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+		return ERR_PTR(ret);
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+	}
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-	return clk;
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+	return hw;
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 }
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+EXPORT_SYMBOL_GPL(clk_hw_register_gate2);