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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/x86/kernel/cpu/perfctr-watchdog.c
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@@ -46,6 +46,7 @@
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 {
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 	/* returns the bit offset of the performance counter register */
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 	switch (boot_cpu_data.x86_vendor) {
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+	case X86_VENDOR_HYGON:
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 	case X86_VENDOR_AMD:
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 		if (msr >= MSR_F15H_PERF_CTR)
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 			return (msr - MSR_F15H_PERF_CTR) >> 1;
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@@ -62,6 +63,10 @@
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 		case 15:
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 			return msr - MSR_P4_BPU_PERFCTR0;
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 		}
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+		break;
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+	case X86_VENDOR_ZHAOXIN:
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+	case X86_VENDOR_CENTAUR:
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+		return msr - MSR_ARCH_PERFMON_PERFCTR0;
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 	}
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 	return 0;
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 }
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@@ -74,6 +79,7 @@
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 {
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 	/* returns the bit offset of the event selection register */
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 	switch (boot_cpu_data.x86_vendor) {
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+	case X86_VENDOR_HYGON:
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 	case X86_VENDOR_AMD:
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 		if (msr >= MSR_F15H_PERF_CTL)
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 			return (msr - MSR_F15H_PERF_CTL) >> 1;
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@@ -90,6 +96,10 @@
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 		case 15:
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 			return msr - MSR_P4_BSU_ESCR0;
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 		}
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+		break;
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+	case X86_VENDOR_ZHAOXIN:
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+	case X86_VENDOR_CENTAUR:
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+		return msr - MSR_ARCH_PERFMON_EVENTSEL0;
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 	}
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 	return 0;
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