change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/x86/include/asm/sync_core.h
..
..
@@ -5,6 +5,88 @@
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 #include <linux/preempt.h>
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 #include <asm/processor.h>
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 #include <asm/cpufeature.h>
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+#include <asm/special_insns.h>
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+
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+#ifdef CONFIG_X86_32
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+static inline void iret_to_self(void)
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+{
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+	asm volatile (
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+		"pushfl\n\t"
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+		"pushl %%cs\n\t"
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+		"pushl $1f\n\t"
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+		"iret\n\t"
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+		"1:"
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+		: ASM_CALL_CONSTRAINT : : "memory");
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+}
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+#else
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+static inline void iret_to_self(void)
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+{
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+	unsigned int tmp;
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+
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+	asm volatile (
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+		"mov %%ss, %0\n\t"
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+		"pushq %q0\n\t"
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+		"pushq %%rsp\n\t"
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+		"addq $8, (%%rsp)\n\t"
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+		"pushfq\n\t"
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+		"mov %%cs, %0\n\t"
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+		"pushq %q0\n\t"
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+		"pushq $1f\n\t"
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+		"iretq\n\t"
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+		"1:"
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+		: "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
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+}
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+#endif /* CONFIG_X86_32 */
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+
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+/*
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+ * This function forces the icache and prefetched instruction stream to
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+ * catch up with reality in two very specific cases:
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+ *
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+ *  a) Text was modified using one virtual address and is about to be executed
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+ *     from the same physical page at a different virtual address.
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+ *
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+ *  b) Text was modified on a different CPU, may subsequently be
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+ *     executed on this CPU, and you want to make sure the new version
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+ *     gets executed.  This generally means you're calling this in an IPI.
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+ *
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+ * If you're calling this for a different reason, you're probably doing
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+ * it wrong.
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+ *
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+ * Like all of Linux's memory ordering operations, this is a
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+ * compiler barrier as well.
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+ */
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+static inline void sync_core(void)
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+{
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+	/*
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+	 * The SERIALIZE instruction is the most straightforward way to
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+	 * do this, but it is not universally available.
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+	 */
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+	if (static_cpu_has(X86_FEATURE_SERIALIZE)) {
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+		serialize();
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+		return;
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+	}
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+
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+	/*
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+	 * For all other processors, there are quite a few ways to do this.
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+	 * IRET-to-self is nice because it works on every CPU, at any CPL
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+	 * (so it's compatible with paravirtualization), and it never exits
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+	 * to a hypervisor.  The only downsides are that it's a bit slow
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+	 * (it seems to be a bit more than 2x slower than the fastest
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+	 * options) and that it unmasks NMIs.  The "push %cs" is needed,
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+	 * because in paravirtual environments __KERNEL_CS may not be a
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+	 * valid CS value when we do IRET directly.
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+	 *
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+	 * In case NMI unmasking or performance ever becomes a problem,
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+	 * the next best option appears to be MOV-to-CR2 and an
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+	 * unconditional jump.  That sequence also works on all CPUs,
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+	 * but it will fault at CPL3 (i.e. Xen PV).
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+	 *
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+	 * CPUID is the conventional way, but it's nasty: it doesn't
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+	 * exist on some 486-like CPUs, and it usually exits to a
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+	 * hypervisor.
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+	 */
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+	iret_to_self();
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+}
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 /*
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  * Ensure that a core serializing instruction is issued before returning