change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/x86/include/asm/sync_bitops.h
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@@ -14,6 +14,8 @@
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  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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  */
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+#include <asm/rmwcc.h>
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+
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 #define ADDR (*(volatile long *)addr)
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 /**
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@@ -29,7 +31,7 @@
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  */
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 static inline void sync_set_bit(long nr, volatile unsigned long *addr)
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 {
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-	asm volatile("lock; bts %1,%0"
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+	asm volatile("lock; " __ASM_SIZE(bts) " %1,%0"
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 		     : "+m" (ADDR)
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 		     : "Ir" (nr)
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 		     : "memory");
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@@ -47,7 +49,7 @@
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  */
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 static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
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 {
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-	asm volatile("lock; btr %1,%0"
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+	asm volatile("lock; " __ASM_SIZE(btr) " %1,%0"
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 		     : "+m" (ADDR)
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 		     : "Ir" (nr)
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 		     : "memory");
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@@ -64,7 +66,7 @@
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  */
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 static inline void sync_change_bit(long nr, volatile unsigned long *addr)
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 {
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-	asm volatile("lock; btc %1,%0"
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+	asm volatile("lock; " __ASM_SIZE(btc) " %1,%0"
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 		     : "+m" (ADDR)
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 		     : "Ir" (nr)
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 		     : "memory");
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@@ -78,14 +80,9 @@
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  * This operation is atomic and cannot be reordered.
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  * It also implies a memory barrier.
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  */
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-static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
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+static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr)
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 {
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-	unsigned char oldbit;
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-
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-	asm volatile("lock; bts %2,%1\n\tsetc %0"
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-		     : "=qm" (oldbit), "+m" (ADDR)
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-		     : "Ir" (nr) : "memory");
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-	return oldbit;
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+	return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(bts), *addr, c, "Ir", nr);
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 }
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 /**
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@@ -98,12 +95,7 @@
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  */
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 static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
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 {
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-	unsigned char oldbit;
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-
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-	asm volatile("lock; btr %2,%1\n\tsetc %0"
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-		     : "=qm" (oldbit), "+m" (ADDR)
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-		     : "Ir" (nr) : "memory");
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-	return oldbit;
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+	return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btr), *addr, c, "Ir", nr);
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 }
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 /**
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@@ -116,12 +108,7 @@
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  */
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 static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr)
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 {
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-	unsigned char oldbit;
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-
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-	asm volatile("lock; btc %2,%1\n\tsetc %0"
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-		     : "=qm" (oldbit), "+m" (ADDR)
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-		     : "Ir" (nr) : "memory");
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-	return oldbit;
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+	return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btc), *addr, c, "Ir", nr);
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 }
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 #define sync_test_bit(nr, addr) test_bit(nr, addr)