change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/x86/include/asm/msr.h
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@@ -60,22 +60,20 @@
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 #define EAX_EDX_RET(val, low, high)	"=A" (val)
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 #endif
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-#ifdef CONFIG_TRACEPOINTS
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 /*
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  * Be very careful with includes. This header is prone to include loops.
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  */
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 #include <asm/atomic.h>
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 #include <linux/tracepoint-defs.h>
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-extern struct tracepoint __tracepoint_read_msr;
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-extern struct tracepoint __tracepoint_write_msr;
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-extern struct tracepoint __tracepoint_rdpmc;
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-#define msr_tracepoint_active(t) static_key_false(&(t).key)
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+#ifdef CONFIG_TRACEPOINTS
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+DECLARE_TRACEPOINT(read_msr);
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+DECLARE_TRACEPOINT(write_msr);
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+DECLARE_TRACEPOINT(rdpmc);
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 extern void do_trace_write_msr(unsigned int msr, u64 val, int failed);
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 extern void do_trace_read_msr(unsigned int msr, u64 val, int failed);
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 extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed);
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 #else
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-#define msr_tracepoint_active(t) false
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 static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {}
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 static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {}
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 static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {}
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@@ -128,7 +126,7 @@
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 	val = __rdmsr(msr);
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-	if (msr_tracepoint_active(__tracepoint_read_msr))
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+	if (tracepoint_enabled(read_msr))
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 		do_trace_read_msr(msr, val, 0);
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 	return val;
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@@ -150,7 +148,7 @@
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 		     _ASM_EXTABLE(2b, 3b)
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 		     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
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 		     : "c" (msr), [fault] "i" (-EIO));
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-	if (msr_tracepoint_active(__tracepoint_read_msr))
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+	if (tracepoint_enabled(read_msr))
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 		do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
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 	return EAX_EDX_VAL(val, low, high);
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 }
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@@ -161,7 +159,7 @@
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 {
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 	__wrmsr(msr, low, high);
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-	if (msr_tracepoint_active(__tracepoint_write_msr))
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+	if (tracepoint_enabled(write_msr))
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 		do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
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 }
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@@ -181,7 +179,7 @@
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 		     : "c" (msr), "0" (low), "d" (high),
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 		       [fault] "i" (-EIO)
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 		     : "memory");
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-	if (msr_tracepoint_active(__tracepoint_write_msr))
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+	if (tracepoint_enabled(write_msr))
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 		do_trace_write_msr(msr, ((u64)high << 32 | low), err);
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 	return err;
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 }
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@@ -217,6 +215,8 @@
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  */
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 static __always_inline unsigned long long rdtsc_ordered(void)
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 {
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+	DECLARE_ARGS(val, low, high);
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+
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 	/*
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 	 * The RDTSC instruction is not ordered relative to memory
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 	 * access.  The Intel SDM and the AMD APM are both vague on this
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@@ -227,9 +227,18 @@
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 	 * ordering guarantees as reading from a global memory location
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 	 * that some other imaginary CPU is updating continuously with a
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 	 * time stamp.
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+	 *
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+	 * Thus, use the preferred barrier on the respective CPU, aiming for
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+	 * RDTSCP as the default.
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 	 */
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-	barrier_nospec();
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-	return rdtsc();
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+	asm volatile(ALTERNATIVE_2("rdtsc",
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+				   "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC,
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+				   "rdtscp", X86_FEATURE_RDTSCP)
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+			: EAX_EDX_RET(val, low, high)
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+			/* RDTSCP clobbers ECX with MSR_TSC_AUX. */
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+			:: "ecx");
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+
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+	return EAX_EDX_VAL(val, low, high);
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 }
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 static inline unsigned long long native_read_pmc(int counter)
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@@ -237,12 +246,12 @@
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 	DECLARE_ARGS(val, low, high);
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 	asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
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-	if (msr_tracepoint_active(__tracepoint_rdpmc))
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+	if (tracepoint_enabled(rdpmc))
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 		do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
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 	return EAX_EDX_VAL(val, low, high);
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 }
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-#ifdef CONFIG_PARAVIRT
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+#ifdef CONFIG_PARAVIRT_XXL
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 #include <asm/paravirt.h>
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 #else
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 #include <linux/errno.h>
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@@ -305,7 +314,7 @@
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 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
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-#endif	/* !CONFIG_PARAVIRT */
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+#endif	/* !CONFIG_PARAVIRT_XXL */
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 /*
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  * 64-bit version of wrmsr_safe():