| .. | .. | 
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| 12 | 12 |  	 * stale TLB entries and, especially if we're flushing global | 
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| 13 | 13 |  	 * mappings, we don't want the compiler to reorder any subsequent | 
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| 14 | 14 |  	 * memory accesses before the TLB flush. | 
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| 15 |  | -	 *  | 
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| 16 |  | -	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and  | 
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| 17 |  | -	 * invpcid (%rcx), %rax in long mode.  | 
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| 18 | 15 |  	 */ | 
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| 19 |  | -	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"  | 
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| 20 |  | -		      : : "m" (desc), "a" (type), "c" (&desc) : "memory");  | 
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 | 16 | +	asm volatile("invpcid %[desc], %[type]"  | 
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 | 17 | +		     :: [desc] "m" (desc), [type] "r" (type) : "memory");  | 
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| 21 | 18 |  } | 
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| 22 | 19 |   | 
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| 23 | 20 |  #define INVPCID_TYPE_INDIV_ADDR		0 | 
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