change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/x86/include/asm/fpu/types.h
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@@ -114,6 +114,12 @@
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 	XFEATURE_Hi16_ZMM,
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 	XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
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 	XFEATURE_PKRU,
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+	XFEATURE_PASID,
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+	XFEATURE_RSRVD_COMP_11,
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+	XFEATURE_RSRVD_COMP_12,
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+	XFEATURE_RSRVD_COMP_13,
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+	XFEATURE_RSRVD_COMP_14,
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+	XFEATURE_LBR,
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 	XFEATURE_MAX,
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 };
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@@ -128,6 +134,8 @@
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 #define XFEATURE_MASK_Hi16_ZMM		(1 << XFEATURE_Hi16_ZMM)
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 #define XFEATURE_MASK_PT		(1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
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 #define XFEATURE_MASK_PKRU		(1 << XFEATURE_PKRU)
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+#define XFEATURE_MASK_PASID		(1 << XFEATURE_PASID)
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+#define XFEATURE_MASK_LBR		(1 << XFEATURE_LBR)
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 #define XFEATURE_MASK_FPSSE		(XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
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 #define XFEATURE_MASK_AVX512		(XFEATURE_MASK_OPMASK \
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@@ -229,6 +237,34 @@
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 	u32				pad;
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 } __packed;
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+/*
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+ * State component 15: Architectural LBR configuration state.
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+ * The size of Arch LBR state depends on the number of LBRs (lbr_depth).
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+ */
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+
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+struct lbr_entry {
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+	u64 from;
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+	u64 to;
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+	u64 info;
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+};
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+
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+struct arch_lbr_state {
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+	u64 lbr_ctl;
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+	u64 lbr_depth;
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+	u64 ler_from;
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+	u64 ler_to;
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+	u64 ler_info;
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+	struct lbr_entry		entries[];
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+} __packed;
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+
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+/*
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+ * State component 10 is supervisor state used for context-switching the
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+ * PASID state.
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+ */
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+struct ia32_pasid_state {
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+	u64 pasid;
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+} __packed;
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+
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 struct xstate_header {
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 	u64				xfeatures;
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 	u64				xcomp_bv;
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@@ -294,13 +330,11 @@
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 	unsigned int			last_cpu;
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 	/*
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-	 * @initialized:
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+	 * @avx512_timestamp:
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 	 *
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-	 * This flag indicates whether this context is initialized: if the task
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-	 * is not running then we can restore from this context, if the task
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-	 * is running then we should save into this context.
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+	 * Records the timestamp of AVX512 use during last context switch.
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 	 */
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-	unsigned char			initialized;
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+	unsigned long			avx512_timestamp;
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 	/*
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 	 * @state: