change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/powerpc/perf/power9-pmu.c
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@@ -1,14 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Performance counter support for POWER9 processors.
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  *
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  * Copyright 2009 Paul Mackerras, IBM Corporation.
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  * Copyright 2013 Michael Ellerman, IBM Corporation.
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  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or later version.
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  */
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 #define pr_fmt(fmt)	"power9-pmu: " fmt
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@@ -63,16 +59,8 @@
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  *	MMCRA[9:11] = thresh_cmp[0:2]
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  *	MMCRA[12:18] = thresh_cmp[3:9]
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  *
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- * if unit == 6 or unit == 7
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- *	MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
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- * else if unit == 8 or unit == 9:
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- *	if cache_sel[0] == 0: # L3 bank
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- *		MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
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- *	else if cache_sel[0] == 1:
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- *		MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
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- * else if cache_sel[1]: # L1 event
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- *	MMCR1[16] = cache_sel[2]
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- *	MMCR1[17] = cache_sel[3]
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+ * MMCR1[16] = cache_sel[2]
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+ * MMCR1[17] = cache_sel[3]
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  *
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  * if mark:
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  *	MMCRA[63]    = 1		(SAMPLE_ENABLE)
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@@ -101,6 +89,8 @@
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 #define POWER9_MMCRA_IFM2		0x0000000080000000UL
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 #define POWER9_MMCRA_IFM3		0x00000000C0000000UL
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 #define POWER9_MMCRA_BHRB_MASK		0x00000000C0000000UL
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+
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+extern u64 PERF_REG_EXTENDED_MASK;
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 /* Nasty Power9 specific hack */
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 #define PVR_POWER9_CUMULUS		0x00002000
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@@ -143,11 +133,11 @@
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 /* Table of alternatives, sorted by column 0 */
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 static const unsigned int power9_event_alternatives[][MAX_ALT] = {
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-	{ PM_INST_DISP,			PM_INST_DISP_ALT },
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-	{ PM_RUN_CYC_ALT,		PM_RUN_CYC },
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-	{ PM_RUN_INST_CMPL_ALT,		PM_RUN_INST_CMPL },
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-	{ PM_LD_MISS_L1,		PM_LD_MISS_L1_ALT },
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 	{ PM_BR_2PATH,			PM_BR_2PATH_ALT },
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+	{ PM_INST_DISP,			PM_INST_DISP_ALT },
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+	{ PM_RUN_CYC_ALT,               PM_RUN_CYC },
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+	{ PM_LD_MISS_L1,                PM_LD_MISS_L1_ALT },
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+	{ PM_RUN_INST_CMPL_ALT,         PM_RUN_INST_CMPL },
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 };
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 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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@@ -169,6 +159,8 @@
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 GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);
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 GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);
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 GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1_FIN);
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+GENERIC_EVENT_ATTR(mem-loads,			MEM_LOADS);
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+GENERIC_EVENT_ATTR(mem-stores,			MEM_STORES);
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 CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1_FIN);
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 CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
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@@ -180,8 +172,6 @@
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 CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);
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 CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);
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 CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);
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-CACHE_EVENT_ATTR(LLC-store-misses,		PM_L2_ST_MISS);
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-CACHE_EVENT_ATTR(LLC-stores,			PM_L2_ST);
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 CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);
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 CACHE_EVENT_ATTR(branch-loads,			PM_BR_CMPL);
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 CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);
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@@ -196,6 +186,8 @@
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 	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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 	GENERIC_EVENT_PTR(PM_LD_REF_L1),
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 	GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
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+	GENERIC_EVENT_PTR(MEM_LOADS),
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+	GENERIC_EVENT_PTR(MEM_STORES),
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 	CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
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 	CACHE_EVENT_PTR(PM_LD_REF_L1),
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 	CACHE_EVENT_PTR(PM_L1_PREF),
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@@ -206,8 +198,6 @@
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 	CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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 	CACHE_EVENT_PTR(PM_DATA_FROM_L3),
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 	CACHE_EVENT_PTR(PM_L3_PREF_ALL),
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-	CACHE_EVENT_PTR(PM_L2_ST_MISS),
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-	CACHE_EVENT_PTR(PM_L2_ST),
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 	CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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 	CACHE_EVENT_PTR(PM_BR_CMPL),
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 	CACHE_EVENT_PTR(PM_DTLB_MISS),
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@@ -322,7 +312,7 @@
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  * 0 means not supported, -1 means nonsensical, other values
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  * are event codes.
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  */
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-static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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+static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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 	[ C(L1D) ] = {
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 		[ C(OP_READ) ] = {
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 			[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
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@@ -357,8 +347,8 @@
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 			[ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
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 		},
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 		[ C(OP_WRITE) ] = {
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-			[ C(RESULT_ACCESS) ] = PM_L2_ST,
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-			[ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
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+			[ C(RESULT_ACCESS) ] = 0,
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+			[ C(RESULT_MISS)   ] = 0,
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 		},
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 		[ C(OP_PREFETCH) ] = {
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 			[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
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@@ -430,6 +420,8 @@
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 	.n_counter		= MAX_PMU_COUNTERS,
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 	.add_fields		= ISA207_ADD_FIELDS,
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 	.test_adder		= ISA207_TEST_ADDER,
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+	.group_constraint_mask	= CNST_CACHE_PMC4_MASK,
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+	.group_constraint_val	= CNST_CACHE_PMC4_VAL,
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 	.compute_mmcr		= isa207_compute_mmcr,
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 	.config_bhrb		= power9_config_bhrb,
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 	.bhrb_filter_map	= power9_bhrb_filter_map,
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@@ -444,9 +436,10 @@
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 	.cache_events		= &power9_cache_events,
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 	.attr_groups		= power9_pmu_attr_groups,
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 	.bhrb_nr		= 32,
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+	.capabilities           = PERF_PMU_CAP_EXTENDED_REGS,
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 };
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-static int __init init_power9_pmu(void)
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+int init_power9_pmu(void)
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 {
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 	int rc = 0;
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 	unsigned int pvr = mfspr(SPRN_PVR);
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@@ -467,6 +460,9 @@
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 		}
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 	}
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+	/* Set the PERF_REG_EXTENDED_MASK here */
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+	PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
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+
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 	rc = register_power_pmu(&power9_pmu);
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 	if (rc)
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 		return rc;
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@@ -476,4 +472,3 @@
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 	return 0;
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 }
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-early_initcall(init_power9_pmu);