change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/powerpc/perf/power9-events-list.h
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@@ -1,12 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Performance counter support for POWER9 processors.
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  *
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  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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 /*
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@@ -63,8 +59,6 @@
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 /* Instruction Dispatched */
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 EVENT(PM_INST_DISP,				0x200f2)
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 EVENT(PM_INST_DISP_ALT,				0x300f2)
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-/* Alternate Branch event code */
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-EVENT(PM_BR_CMPL_ALT,				0x10012)
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 /* Branch event that are not strongly biased */
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 EVENT(PM_BR_2PATH,				0x20036)
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 /* ALternate branch event that are not strongly biased */
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@@ -97,3 +91,27 @@
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 EVENT(PM_DTLB_MISS_16M,				0x4c056)
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 EVENT(PM_DTLB_MISS_1G,				0x4c05a)
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 EVENT(PM_MRK_DTLB_MISS_16M,			0x4c15e)
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+
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+/*
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+ * Memory Access Events
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+ *
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+ * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
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+ * To enable capturing of memory profiling, these MMCRA bits
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+ * needs to be programmed and corresponding raw event format
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+ * encoding.
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+ *
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+ * MMCRA bits encoding needed are
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+ *     SM (Sampling Mode)
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+ *     EM (Eligibility for Random Sampling)
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+ *     TECE (Threshold Event Counter Event)
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+ *     TS (Threshold Start Event)
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+ *     TE (Threshold End Event)
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+ *
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+ * Corresponding Raw Encoding bits:
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+ *     sample [EM,SM]
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+ *     thresh_sel (TECE)
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+ *     thresh start (TS)
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+ *     thresh end (TE)
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+ */
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+EVENT(MEM_LOADS,				0x34340401e0)
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+EVENT(MEM_STORES,				0x343c0401e0)