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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/arch/powerpc/perf/isa207-common.h
....@@ -1,12 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright 2009 Paul Mackerras, IBM Corporation.
34  * Copyright 2013 Michael Ellerman, IBM Corporation.
45  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License
8
- * as published by the Free Software Foundation; either version
9
- * 2 of the License, or any later version.
106  */
117 
128 #ifndef _LINUX_POWERPC_PERF_ISA207_COMMON_H_
....@@ -16,6 +12,8 @@
1612 #include <linux/perf_event.h>
1713 #include <asm/firmware.h>
1814 #include <asm/cputable.h>
15
+
16
+#include "internal.h"
1917 
2018 #define EVENT_EBB_MASK		1ull
2119 #define EVENT_EBB_SHIFT		PERF_EVENT_CONFIG_EBB_SHIFT
....@@ -91,6 +89,35 @@
9189 	 EVENT_LINUX_MASK					|	\
9290 	 EVENT_PSEL_MASK))
9391 
92
+/* Contants to support power10 raw encoding format */
93
+#define p10_SDAR_MODE_SHIFT		22
94
+#define p10_SDAR_MODE_MASK		0x3ull
95
+#define p10_SDAR_MODE(v)		(((v) >> p10_SDAR_MODE_SHIFT) & \
96
+					p10_SDAR_MODE_MASK)
97
+#define p10_EVENT_L2L3_SEL_MASK		0x1f
98
+#define p10_L2L3_SEL_SHIFT		3
99
+#define p10_L2L3_EVENT_SHIFT		40
100
+#define p10_EVENT_THRESH_MASK		0xffffull
101
+#define p10_EVENT_CACHE_SEL_MASK	0x3ull
102
+#define p10_EVENT_MMCR3_MASK		0x7fffull
103
+#define p10_EVENT_MMCR3_SHIFT		45
104
+#define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT	9
105
+#define p10_EVENT_RADIX_SCOPE_QUAL_MASK	0x1
106
+#define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT	45
107
+
108
+#define p10_EVENT_VALID_MASK		\
109
+	((p10_SDAR_MODE_MASK   << p10_SDAR_MODE_SHIFT		|	\
110
+	(p10_EVENT_THRESH_MASK  << EVENT_THRESH_SHIFT)		|	\
111
+	(EVENT_SAMPLE_MASK     << EVENT_SAMPLE_SHIFT)		|	\
112
+	(p10_EVENT_CACHE_SEL_MASK  << EVENT_CACHE_SEL_SHIFT)	|	\
113
+	(EVENT_PMC_MASK        << EVENT_PMC_SHIFT)		|	\
114
+	(EVENT_UNIT_MASK       << EVENT_UNIT_SHIFT)		|	\
115
+	(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT)	|	\
116
+	(p10_EVENT_MMCR3_MASK  << p10_EVENT_MMCR3_SHIFT)	|	\
117
+	(EVENT_MARKED_MASK     << EVENT_MARKED_SHIFT)		|	\
118
+	(p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT)	|	\
119
+	 EVENT_LINUX_MASK					|	\
120
+	EVENT_PSEL_MASK))
94121 /*
95122  * Layout of constraint bits:
96123  *
....@@ -102,9 +129,9 @@
102129  *
103130  *        28        24        20        16        12         8         4         0
104131  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
105
- *               [ ] |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
106
- *                |  |    |                     |
107
- *      BHRB IFM -*  |    |                     |      Count of events for each PMC.
132
+ *               [ ] |   [ ] |  [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
133
+ *                |  |    |  |                  |
134
+ *      BHRB IFM -*  |    |  |*radix_scope      |      Count of events for each PMC.
108135  *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
109136  *      L1 I/D qualifier -*                     |
110137  *                     nc - number of counters -*
....@@ -122,6 +149,9 @@
122149 #define CNST_THRESH_VAL(v)	(((v) & EVENT_THRESH_MASK) << 32)
123150 #define CNST_THRESH_MASK	CNST_THRESH_VAL(EVENT_THRESH_MASK)
124151 
152
+#define CNST_THRESH_CTL_SEL_VAL(v)	(((v) & 0x7ffull) << 32)
153
+#define CNST_THRESH_CTL_SEL_MASK	CNST_THRESH_CTL_SEL_VAL(0x7ff)
154
+
125155 #define CNST_EBB_VAL(v)		(((v) & EVENT_EBB_MASK) << 24)
126156 #define CNST_EBB_MASK		CNST_EBB_VAL(EVENT_EBB_MASK)
127157 
....@@ -133,6 +163,17 @@
133163 
134164 #define CNST_SAMPLE_VAL(v)	(((v) & EVENT_SAMPLE_MASK) << 16)
135165 #define CNST_SAMPLE_MASK	CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
166
+
167
+#define CNST_CACHE_GROUP_VAL(v)	(((v) & 0xffull) << 55)
168
+#define CNST_CACHE_GROUP_MASK	CNST_CACHE_GROUP_VAL(0xff)
169
+#define CNST_CACHE_PMC4_VAL	(1ull << 54)
170
+#define CNST_CACHE_PMC4_MASK	CNST_CACHE_PMC4_VAL
171
+
172
+#define CNST_L2L3_GROUP_VAL(v)	(((v) & 0x1full) << 55)
173
+#define CNST_L2L3_GROUP_MASK	CNST_L2L3_GROUP_VAL(0x1f)
174
+
175
+#define CNST_RADIX_SCOPE_GROUP_VAL(v)	(((v) & 0x1ull) << 21)
176
+#define CNST_RADIX_SCOPE_GROUP_MASK	CNST_RADIX_SCOPE_GROUP_VAL(1)
136177 
137178 /*
138179  * For NC we are counting up to 4 events. This requires three bits, and we need
....@@ -190,7 +231,11 @@
190231 #define MMCRA_THR_CTR_EXP(v)		(((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
191232 						MMCRA_THR_CTR_EXP_MASK)
192233 
193
-/* MMCR1 Threshold Compare bit constant for power9 */
234
+#define P10_MMCRA_THR_CTR_MANT_MASK	0xFFul
235
+#define P10_MMCRA_THR_CTR_MANT(v)	(((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
236
+						P10_MMCRA_THR_CTR_MANT_MASK)
237
+
238
+/* MMCRA Threshold Compare bit constant for power9 */
194239 #define p9_MMCRA_THR_CMP_SHIFT	45
195240 
196241 /* Bits in MMCR2 for PowerISA v2.07 */
....@@ -200,6 +245,9 @@
200245 
201246 #define MAX_ALT				2
202247 #define MAX_PMU_COUNTERS		6
248
+
249
+/* Bits in MMCR3 for PowerISA v3.10 */
250
+#define MMCR3_SHIFT(pmc)		(49 - (15 * ((pmc) - 1)))
203251 
204252 #define ISA207_SIER_TYPE_SHIFT		15
205253 #define ISA207_SIER_TYPE_MASK		(0x7ull << ISA207_SIER_TYPE_SHIFT)
....@@ -216,9 +264,9 @@
216264 
217265 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
218266 int isa207_compute_mmcr(u64 event[], int n_ev,
219
-				unsigned int hwc[], unsigned long mmcr[],
267
+				unsigned int hwc[], struct mmcr_regs *mmcr,
220268 				struct perf_event *pevents[]);
221
-void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]);
269
+void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);
222270 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
223271 					const unsigned int ev_alt[][MAX_ALT]);
224272 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,