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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/arch/powerpc/kvm/book3s_hv_interrupts.S
....@@ -1,16 +1,5 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License, version 2, as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
143  *
154  * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
165  *
....@@ -64,63 +53,21 @@
6453 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
6554 
6655 	/* Save host PMU registers */
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-BEGIN_FTR_SECTION
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-	/* Work around P8 PMAE bug */
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-	li	r3, -1
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-	clrrdi	r3, r3, 10
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-	mfspr	r8, SPRN_MMCR2
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-	mtspr	SPRN_MMCR2, r3		/* freeze all counters using MMCR2 */
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-	isync
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-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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-	li	r3, 1
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-	sldi	r3, r3, 31		/* MMCR0_FC (freeze counters) bit */
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-	mfspr	r7, SPRN_MMCR0		/* save MMCR0 */
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-	mtspr	SPRN_MMCR0, r3		/* freeze all counters, disable interrupts */
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-	mfspr	r6, SPRN_MMCRA
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-	/* Clear MMCRA in order to disable SDAR updates */
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-	li	r5, 0
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-	mtspr	SPRN_MMCRA, r5
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-	isync
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-	lbz	r5, PACA_PMCINUSE(r13)	/* is the host using the PMU? */
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-	cmpwi	r5, 0
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-	beq	31f			/* skip if not */
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-	mfspr	r5, SPRN_MMCR1
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-	mfspr	r9, SPRN_SIAR
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-	mfspr	r10, SPRN_SDAR
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-	std	r7, HSTATE_MMCR0(r13)
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-	std	r5, HSTATE_MMCR1(r13)
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-	std	r6, HSTATE_MMCRA(r13)
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-	std	r9, HSTATE_SIAR(r13)
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-	std	r10, HSTATE_SDAR(r13)
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-BEGIN_FTR_SECTION
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-	mfspr	r9, SPRN_SIER
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-	std	r8, HSTATE_MMCR2(r13)
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-	std	r9, HSTATE_SIER(r13)
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-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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-	mfspr	r3, SPRN_PMC1
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-	mfspr	r5, SPRN_PMC2
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-	mfspr	r6, SPRN_PMC3
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-	mfspr	r7, SPRN_PMC4
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-	mfspr	r8, SPRN_PMC5
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-	mfspr	r9, SPRN_PMC6
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-	stw	r3, HSTATE_PMC1(r13)
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-	stw	r5, HSTATE_PMC2(r13)
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-	stw	r6, HSTATE_PMC3(r13)
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-	stw	r7, HSTATE_PMC4(r13)
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-	stw	r8, HSTATE_PMC5(r13)
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-	stw	r9, HSTATE_PMC6(r13)
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-31:
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+	bl	kvmhv_save_host_pmu
11357 
11458 	/*
11559 	 * Put whatever is in the decrementer into the
11660 	 * hypervisor decrementer.
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+	 * Because of a hardware deviation in P8 and P9,
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+	 * we need to set LPCR[HDICE] before writing HDEC.
11763 	 */
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-BEGIN_FTR_SECTION
11964 	ld	r5, HSTATE_KVM_VCORE(r13)
12065 	ld	r6, VCORE_KVM(r5)
12166 	ld	r9, KVM_HOST_LPCR(r6)
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-	andis.	r9, r9, LPCR_LD@h
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-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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+	ori	r8, r9, LPCR_HDICE
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+	mtspr	SPRN_LPCR, r8
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+	isync
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+	andis.	r0, r9, LPCR_LD@h
12471 	mfspr	r8,SPRN_DEC
12572 	mftb	r7
12673 BEGIN_FTR_SECTION
....@@ -161,3 +108,59 @@
161108 	ld	r0, PPC_LR_STKOFF(r1)
162109 	mtlr	r0
163110 	blr
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+
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+_GLOBAL(kvmhv_save_host_pmu)
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+BEGIN_FTR_SECTION
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+	/* Work around P8 PMAE bug */
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+	li	r3, -1
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+	clrrdi	r3, r3, 10
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+	mfspr	r8, SPRN_MMCR2
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+	mtspr	SPRN_MMCR2, r3		/* freeze all counters using MMCR2 */
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+	isync
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+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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+	li	r3, 1
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+	sldi	r3, r3, 31		/* MMCR0_FC (freeze counters) bit */
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+	mfspr	r7, SPRN_MMCR0		/* save MMCR0 */
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+	mtspr	SPRN_MMCR0, r3		/* freeze all counters, disable interrupts */
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+	mfspr	r6, SPRN_MMCRA
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+	/* Clear MMCRA in order to disable SDAR updates */
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+	li	r5, 0
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+	mtspr	SPRN_MMCRA, r5
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+	isync
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+	lbz	r5, PACA_PMCINUSE(r13)	/* is the host using the PMU? */
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+	cmpwi	r5, 0
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+	beq	31f			/* skip if not */
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+	mfspr	r5, SPRN_MMCR1
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+	mfspr	r9, SPRN_SIAR
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+	mfspr	r10, SPRN_SDAR
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+	std	r7, HSTATE_MMCR0(r13)
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+	std	r5, HSTATE_MMCR1(r13)
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+	std	r6, HSTATE_MMCRA(r13)
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+	std	r9, HSTATE_SIAR(r13)
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+	std	r10, HSTATE_SDAR(r13)
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+BEGIN_FTR_SECTION
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+	mfspr	r9, SPRN_SIER
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+	std	r8, HSTATE_MMCR2(r13)
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+	std	r9, HSTATE_SIER(r13)
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+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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+BEGIN_FTR_SECTION
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+	mfspr	r5, SPRN_MMCR3
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+	mfspr	r6, SPRN_SIER2
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+	mfspr	r7, SPRN_SIER3
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+	std	r5, HSTATE_MMCR3(r13)
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+	std	r6, HSTATE_SIER2(r13)
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+	std	r7, HSTATE_SIER3(r13)
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+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
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+	mfspr	r3, SPRN_PMC1
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+	mfspr	r5, SPRN_PMC2
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+	mfspr	r6, SPRN_PMC3
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+	mfspr	r7, SPRN_PMC4
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+	mfspr	r8, SPRN_PMC5
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+	mfspr	r9, SPRN_PMC6
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+	stw	r3, HSTATE_PMC1(r13)
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+	stw	r5, HSTATE_PMC2(r13)
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+	stw	r6, HSTATE_PMC3(r13)
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+	stw	r7, HSTATE_PMC4(r13)
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+	stw	r8, HSTATE_PMC5(r13)
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+	stw	r9, HSTATE_PMC6(r13)
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+31:	blr