forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/arch/arm64/include/uapi/asm/ptrace.h
....@@ -23,7 +23,7 @@
2323 #include <linux/types.h>
2424 
2525 #include <asm/hwcap.h>
26
-#include <asm/sigcontext.h>
26
+#include <asm/sve_context.h>
2727 
2828 
2929 /*
....@@ -46,14 +46,18 @@
4646 #define PSR_I_BIT	0x00000080
4747 #define PSR_A_BIT	0x00000100
4848 #define PSR_D_BIT	0x00000200
49
+#define PSR_BTYPE_MASK	0x00000c00
4950 #define PSR_SSBS_BIT	0x00001000
5051 #define PSR_PAN_BIT	0x00400000
5152 #define PSR_UAO_BIT	0x00800000
5253 #define PSR_DIT_BIT	0x01000000
54
+#define PSR_TCO_BIT	0x02000000
5355 #define PSR_V_BIT	0x10000000
5456 #define PSR_C_BIT	0x20000000
5557 #define PSR_Z_BIT	0x40000000
5658 #define PSR_N_BIT	0x80000000
59
+
60
+#define PSR_BTYPE_SHIFT		10
5761 
5862 /*
5963  * Groups of PSR bits
....@@ -63,6 +67,18 @@
6367 #define PSR_x		0x0000ff00	/* Extension		*/
6468 #define PSR_c		0x000000ff	/* Control		*/
6569 
70
+/* Convenience names for the values of PSTATE.BTYPE */
71
+#define PSR_BTYPE_NONE		(0b00 << PSR_BTYPE_SHIFT)
72
+#define PSR_BTYPE_JC		(0b01 << PSR_BTYPE_SHIFT)
73
+#define PSR_BTYPE_C		(0b10 << PSR_BTYPE_SHIFT)
74
+#define PSR_BTYPE_J		(0b11 << PSR_BTYPE_SHIFT)
75
+
76
+/* syscall emulation path in ptrace */
77
+#define PTRACE_SYSEMU		  31
78
+#define PTRACE_SYSEMU_SINGLESTEP  32
79
+/* MTE allocation tag access */
80
+#define PTRACE_PEEKMTETAGS	  33
81
+#define PTRACE_POKEMTETAGS	  34
6682 
6783 #ifndef __ASSEMBLY__
6884 
....@@ -129,9 +145,9 @@
129145  */
130146 
131147 /* Offset from the start of struct user_sve_header to the register data */
132
-#define SVE_PT_REGS_OFFSET					\
133
-	((sizeof(struct user_sve_header) + (SVE_VQ_BYTES - 1))	\
134
-		/ SVE_VQ_BYTES * SVE_VQ_BYTES)
148
+#define SVE_PT_REGS_OFFSET						\
149
+	((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1))	\
150
+		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
135151 
136152 /*
137153  * The register data content and layout depends on the value of the
....@@ -175,41 +191,42 @@
175191  *	FPCR	uint32_t			FPCR
176192  *
177193  * Additional data might be appended in the future.
194
+ *
195
+ * The Z-, P- and FFR registers are represented in memory in an endianness-
196
+ * invariant layout which differs from the layout used for the FPSIMD
197
+ * V-registers on big-endian systems: see sigcontext.h for more explanation.
178198  */
179199 
180
-#define SVE_PT_SVE_ZREG_SIZE(vq)	SVE_SIG_ZREG_SIZE(vq)
181
-#define SVE_PT_SVE_PREG_SIZE(vq)	SVE_SIG_PREG_SIZE(vq)
182
-#define SVE_PT_SVE_FFR_SIZE(vq)		SVE_SIG_FFR_SIZE(vq)
200
+#define SVE_PT_SVE_ZREG_SIZE(vq)	__SVE_ZREG_SIZE(vq)
201
+#define SVE_PT_SVE_PREG_SIZE(vq)	__SVE_PREG_SIZE(vq)
202
+#define SVE_PT_SVE_FFR_SIZE(vq)		__SVE_FFR_SIZE(vq)
183203 #define SVE_PT_SVE_FPSR_SIZE		sizeof(__u32)
184204 #define SVE_PT_SVE_FPCR_SIZE		sizeof(__u32)
185
-
186
-#define __SVE_SIG_TO_PT(offset) \
187
-	((offset) - SVE_SIG_REGS_OFFSET + SVE_PT_REGS_OFFSET)
188205 
189206 #define SVE_PT_SVE_OFFSET		SVE_PT_REGS_OFFSET
190207 
191208 #define SVE_PT_SVE_ZREGS_OFFSET \
192
-	__SVE_SIG_TO_PT(SVE_SIG_ZREGS_OFFSET)
209
+	(SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
193210 #define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
194
-	__SVE_SIG_TO_PT(SVE_SIG_ZREG_OFFSET(vq, n))
211
+	(SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
195212 #define SVE_PT_SVE_ZREGS_SIZE(vq) \
196
-	(SVE_PT_SVE_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
213
+	(SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
197214 
198215 #define SVE_PT_SVE_PREGS_OFFSET(vq) \
199
-	__SVE_SIG_TO_PT(SVE_SIG_PREGS_OFFSET(vq))
216
+	(SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
200217 #define SVE_PT_SVE_PREG_OFFSET(vq, n) \
201
-	__SVE_SIG_TO_PT(SVE_SIG_PREG_OFFSET(vq, n))
218
+	(SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
202219 #define SVE_PT_SVE_PREGS_SIZE(vq) \
203
-	(SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - \
220
+	(SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
204221 		SVE_PT_SVE_PREGS_OFFSET(vq))
205222 
206223 #define SVE_PT_SVE_FFR_OFFSET(vq) \
207
-	__SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq))
224
+	(SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
208225 
209226 #define SVE_PT_SVE_FPSR_OFFSET(vq)				\
210227 	((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) +	\
211
-			(SVE_VQ_BYTES - 1))			\
212
-		/ SVE_VQ_BYTES * SVE_VQ_BYTES)
228
+			(__SVE_VQ_BYTES - 1))			\
229
+		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
213230 #define SVE_PT_SVE_FPCR_OFFSET(vq) \
214231 	(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
215232 
....@@ -220,14 +237,34 @@
220237 
221238 #define SVE_PT_SVE_SIZE(vq, flags)					\
222239 	((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE		\
223
-			- SVE_PT_SVE_OFFSET + (SVE_VQ_BYTES - 1))	\
224
-		/ SVE_VQ_BYTES * SVE_VQ_BYTES)
240
+			- SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1))	\
241
+		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
225242 
226243 #define SVE_PT_SIZE(vq, flags)						\
227244 	 (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ?		\
228245 		  SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags)	\
229246 		: SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
230247 
248
+/* pointer authentication masks (NT_ARM_PAC_MASK) */
249
+
250
+struct user_pac_mask {
251
+	__u64		data_mask;
252
+	__u64		insn_mask;
253
+};
254
+
255
+/* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
256
+
257
+struct user_pac_address_keys {
258
+	__uint128_t	apiakey;
259
+	__uint128_t	apibkey;
260
+	__uint128_t	apdakey;
261
+	__uint128_t	apdbkey;
262
+};
263
+
264
+struct user_pac_generic_keys {
265
+	__uint128_t	apgakey;
266
+};
267
+
231268 #endif /* __ASSEMBLY__ */
232269 
233270 #endif /* _UAPI__ASM_PTRACE_H */