change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
..
..
@@ -2,7 +2,7 @@
2
2
 /*
3
3
  * dts file for Xilinx ZynqMP ZCU102 RevA
4
4
  *
5
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
5
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
6
6
  *
7
7
  * Michal Simek <michal.simek@xilinx.com>
8
8
  */
..
..
@@ -10,7 +10,7 @@
10
10
 /dts-v1/;
11
11
 
12
12
 #include "zynqmp.dtsi"
13
-#include "zynqmp-clk.dtsi"
13
+#include "zynqmp-clk-ccf.dtsi"
14
14
 #include <dt-bindings/input/input.h>
15
15
 #include <dt-bindings/gpio/gpio.h>
16
16
 
..
..
@@ -46,7 +46,7 @@
46
46
 			label = "sw19";
47
47
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
48
48
 			linux,code = <KEY_DOWN>;
49
-			gpio-key,wakeup;
49
+			wakeup-source;
50
50
 			autorepeat;
51
51
 		};
52
52
 	};
..
..
@@ -58,6 +58,79 @@
58
58
 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
59
59
 			linux,default-trigger = "heartbeat";
60
60
 		};
61
+	};
62
+
63
+	ina226-u76 {
64
+		compatible = "iio-hwmon";
65
+		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
66
+	};
67
+	ina226-u77 {
68
+		compatible = "iio-hwmon";
69
+		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
70
+	};
71
+	ina226-u78 {
72
+		compatible = "iio-hwmon";
73
+		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
74
+	};
75
+	ina226-u87 {
76
+		compatible = "iio-hwmon";
77
+		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
78
+	};
79
+	ina226-u85 {
80
+		compatible = "iio-hwmon";
81
+		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
82
+	};
83
+	ina226-u86 {
84
+		compatible = "iio-hwmon";
85
+		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
86
+	};
87
+	ina226-u93 {
88
+		compatible = "iio-hwmon";
89
+		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
90
+	};
91
+	ina226-u88 {
92
+		compatible = "iio-hwmon";
93
+		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
94
+	};
95
+	ina226-u15 {
96
+		compatible = "iio-hwmon";
97
+		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
98
+	};
99
+	ina226-u92 {
100
+		compatible = "iio-hwmon";
101
+		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
102
+	};
103
+	ina226-u79 {
104
+		compatible = "iio-hwmon";
105
+		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
106
+	};
107
+	ina226-u81 {
108
+		compatible = "iio-hwmon";
109
+		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
110
+	};
111
+	ina226-u80 {
112
+		compatible = "iio-hwmon";
113
+		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
114
+	};
115
+	ina226-u84 {
116
+		compatible = "iio-hwmon";
117
+		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
118
+	};
119
+	ina226-u16 {
120
+		compatible = "iio-hwmon";
121
+		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
122
+	};
123
+	ina226-u65 {
124
+		compatible = "iio-hwmon";
125
+		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
126
+	};
127
+	ina226-u74 {
128
+		compatible = "iio-hwmon";
129
+		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
130
+	};
131
+	ina226-u75 {
132
+		compatible = "iio-hwmon";
133
+		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
61
134
 	};
62
135
 };
63
136
 
..
..
@@ -105,11 +178,12 @@
105
178
 	status = "okay";
106
179
 	phy-handle = <&phy0>;
107
180
 	phy-mode = "rgmii-id";
108
-	phy0: phy@21 {
181
+	phy0: ethernet-phy@21 {
109
182
 		reg = <21>;
110
183
 		ti,rx-internal-delay = <0x8>;
111
184
 		ti,tx-internal-delay = <0xa>;
112
185
 		ti,fifo-depth = <0x1>;
186
+		ti,dp83867-rxctrl-strap-quirk;
113
187
 	};
114
188
 };
115
189
 
..
..
@@ -124,40 +198,30 @@
124
198
 	tca6416_u97: gpio@20 {
125
199
 		compatible = "ti,tca6416";
126
200
 		reg = <0x20>;
127
-		gpio-controller;
201
+		gpio-controller; /* IRQ not connected */
128
202
 		#gpio-cells = <2>;
129
-		/*
130
-		 * IRQ not connected
131
-		 * Lines:
132
-		 * 0 - PS_GTR_LAN_SEL0
133
-		 * 1 - PS_GTR_LAN_SEL1
134
-		 * 2 - PS_GTR_LAN_SEL2
135
-		 * 3 - PS_GTR_LAN_SEL3
136
-		 * 4 - PCI_CLK_DIR_SEL
137
-		 * 5 - IIC_MUX_RESET_B
138
-		 * 6 - GEM3_EXP_RESET_B
139
-		 * 7, 10 - 17 - not connected
140
-		 */
141
-
142
-		gtr-sel0 {
203
+		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
204
+				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
205
+				"", "", "", "", "", "", "", "", "";
206
+		gtr-sel0-hog {
143
207
 			gpio-hog;
144
208
 			gpios = <0 0>;
145
209
 			output-low; /* PCIE = 0, DP = 1 */
146
210
 			line-name = "sel0";
147
211
 		};
148
-		gtr-sel1 {
212
+		gtr-sel1-hog {
149
213
 			gpio-hog;
150
214
 			gpios = <1 0>;
151
215
 			output-high; /* PCIE = 0, DP = 1 */
152
216
 			line-name = "sel1";
153
217
 		};
154
-		gtr-sel2 {
218
+		gtr-sel2-hog {
155
219
 			gpio-hog;
156
220
 			gpios = <2 0>;
157
221
 			output-high; /* PCIE = 0, USB0 = 1 */
158
222
 			line-name = "sel2";
159
223
 		};
160
-		gtr-sel3 {
224
+		gtr-sel3-hog {
161
225
 			gpio-hog;
162
226
 			gpios = <3 0>;
163
227
 			output-high; /* PCIE = 0, SATA = 1 */
..
..
@@ -168,27 +232,12 @@
168
232
 	tca6416_u61: gpio@21 {
169
233
 		compatible = "ti,tca6416";
170
234
 		reg = <0x21>;
171
-		gpio-controller;
235
+		gpio-controller; /* IRQ not connected */
172
236
 		#gpio-cells = <2>;
173
-		/*
174
-		 * IRQ not connected
175
-		 * Lines:
176
-		 * 0 - VCCPSPLL_EN
177
-		 * 1 - MGTRAVCC_EN
178
-		 * 2 - MGTRAVTT_EN
179
-		 * 3 - VCCPSDDRPLL_EN
180
-		 * 4 - MIO26_PMU_INPUT_LS
181
-		 * 5 - PL_PMBUS_ALERT
182
-		 * 6 - PS_PMBUS_ALERT
183
-		 * 7 - MAXIM_PMBUS_ALERT
184
-		 * 10 - PL_DDR4_VTERM_EN
185
-		 * 11 - PL_DDR4_VPP_2V5_EN
186
-		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
187
-		 * 13 - PS_DIMM_SUSPEND_EN
188
-		 * 14 - PS_DDR4_VTERM_EN
189
-		 * 15 - PS_DDR4_VPP_2V5_EN
190
-		 * 16 - 17 - not connected
191
-		 */
237
+		gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
238
+				"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
239
+				"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
240
+				"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
192
241
 	};
193
242
 
194
243
 	i2c-mux@75 { /* u60 */
..
..
@@ -201,53 +250,73 @@
201
250
 			#size-cells = <0>;
202
251
 			reg = <0>;
203
252
 			/* PS_PMBUS */
204
-			ina226@40 { /* u76 */
253
+			u76: ina226@40 { /* u76 */
205
254
 				compatible = "ti,ina226";
255
+				#io-channel-cells = <1>;
256
+				label = "ina226-u76";
206
257
 				reg = <0x40>;
207
258
 				shunt-resistor = <5000>;
208
259
 			};
209
-			ina226@41 { /* u77 */
260
+			u77: ina226@41 { /* u77 */
210
261
 				compatible = "ti,ina226";
262
+				#io-channel-cells = <1>;
263
+				label = "ina226-u77";
211
264
 				reg = <0x41>;
212
265
 				shunt-resistor = <5000>;
213
266
 			};
214
-			ina226@42 { /* u78 */
267
+			u78: ina226@42 { /* u78 */
215
268
 				compatible = "ti,ina226";
269
+				#io-channel-cells = <1>;
270
+				label = "ina226-u78";
216
271
 				reg = <0x42>;
217
272
 				shunt-resistor = <5000>;
218
273
 			};
219
-			ina226@43 { /* u87 */
274
+			u87: ina226@43 { /* u87 */
220
275
 				compatible = "ti,ina226";
276
+				#io-channel-cells = <1>;
277
+				label = "ina226-u87";
221
278
 				reg = <0x43>;
222
279
 				shunt-resistor = <5000>;
223
280
 			};
224
-			ina226@44 { /* u85 */
281
+			u85: ina226@44 { /* u85 */
225
282
 				compatible = "ti,ina226";
283
+				#io-channel-cells = <1>;
284
+				label = "ina226-u85";
226
285
 				reg = <0x44>;
227
286
 				shunt-resistor = <5000>;
228
287
 			};
229
-			ina226@45 { /* u86 */
288
+			u86: ina226@45 { /* u86 */
230
289
 				compatible = "ti,ina226";
290
+				#io-channel-cells = <1>;
291
+				label = "ina226-u86";
231
292
 				reg = <0x45>;
232
293
 				shunt-resistor = <5000>;
233
294
 			};
234
-			ina226@46 { /* u93 */
295
+			u93: ina226@46 { /* u93 */
235
296
 				compatible = "ti,ina226";
297
+				#io-channel-cells = <1>;
298
+				label = "ina226-u93";
236
299
 				reg = <0x46>;
237
300
 				shunt-resistor = <5000>;
238
301
 			};
239
-			ina226@47 { /* u88 */
302
+			u88: ina226@47 { /* u88 */
240
303
 				compatible = "ti,ina226";
304
+				#io-channel-cells = <1>;
305
+				label = "ina226-u88";
241
306
 				reg = <0x47>;
242
307
 				shunt-resistor = <5000>;
243
308
 			};
244
-			ina226@4a { /* u15 */
309
+			u15: ina226@4a { /* u15 */
245
310
 				compatible = "ti,ina226";
311
+				#io-channel-cells = <1>;
312
+				label = "ina226-u15";
246
313
 				reg = <0x4a>;
247
314
 				shunt-resistor = <5000>;
248
315
 			};
249
-			ina226@4b { /* u92 */
316
+			u92: ina226@4b { /* u92 */
250
317
 				compatible = "ti,ina226";
318
+				#io-channel-cells = <1>;
319
+				label = "ina226-u92";
251
320
 				reg = <0x4b>;
252
321
 				shunt-resistor = <5000>;
253
322
 			};
..
..
@@ -257,43 +326,59 @@
257
326
 			#size-cells = <0>;
258
327
 			reg = <1>;
259
328
 			/* PL_PMBUS */
260
-			ina226@40 { /* u79 */
329
+			u79: ina226@40 { /* u79 */
261
330
 				compatible = "ti,ina226";
331
+				#io-channel-cells = <1>;
332
+				label = "ina226-u79";
262
333
 				reg = <0x40>;
263
334
 				shunt-resistor = <2000>;
264
335
 			};
265
-			ina226@41 { /* u81 */
336
+			u81: ina226@41 { /* u81 */
266
337
 				compatible = "ti,ina226";
338
+				#io-channel-cells = <1>;
339
+				label = "ina226-u81";
267
340
 				reg = <0x41>;
268
341
 				shunt-resistor = <5000>;
269
342
 			};
270
-			ina226@42 { /* u80 */
343
+			u80: ina226@42 { /* u80 */
271
344
 				compatible = "ti,ina226";
345
+				#io-channel-cells = <1>;
346
+				label = "ina226-u80";
272
347
 				reg = <0x42>;
273
348
 				shunt-resistor = <5000>;
274
349
 			};
275
-			ina226@43 { /* u84 */
350
+			u84: ina226@43 { /* u84 */
276
351
 				compatible = "ti,ina226";
352
+				#io-channel-cells = <1>;
353
+				label = "ina226-u84";
277
354
 				reg = <0x43>;
278
355
 				shunt-resistor = <5000>;
279
356
 			};
280
-			ina226@44 { /* u16 */
357
+			u16: ina226@44 { /* u16 */
281
358
 				compatible = "ti,ina226";
359
+				#io-channel-cells = <1>;
360
+				label = "ina226-u16";
282
361
 				reg = <0x44>;
283
362
 				shunt-resistor = <5000>;
284
363
 			};
285
-			ina226@45 { /* u65 */
364
+			u65: ina226@45 { /* u65 */
286
365
 				compatible = "ti,ina226";
366
+				#io-channel-cells = <1>;
367
+				label = "ina226-u65";
287
368
 				reg = <0x45>;
288
369
 				shunt-resistor = <5000>;
289
370
 			};
290
-			ina226@46 { /* u74 */
371
+			u74: ina226@46 { /* u74 */
291
372
 				compatible = "ti,ina226";
373
+				#io-channel-cells = <1>;
374
+				label = "ina226-u74";
292
375
 				reg = <0x46>;
293
376
 				shunt-resistor = <5000>;
294
377
 			};
295
-			ina226@47 { /* u75 */
378
+			u75: ina226@47 { /* u75 */
296
379
 				compatible = "ti,ina226";
380
+				#io-channel-cells = <1>;
381
+				label = "ina226-u75";
297
382
 				reg = <0x47>;
298
383
 				shunt-resistor = <5000>;
299
384
 			};
..
..
@@ -413,6 +498,7 @@
413
498
 				temperature-stability = <50>;
414
499
 				factory-fout = <300000000>;
415
500
 				clock-frequency = <300000000>;
501
+				clock-output-names = "si570_user";
416
502
 			};
417
503
 		};
418
504
 		i2c@3 {
..
..
@@ -426,6 +512,7 @@
426
512
 				temperature-stability = <50>; /* copy from zc702 */
427
513
 				factory-fout = <156250000>;
428
514
 				clock-frequency = <148500000>;
515
+				clock-output-names = "si570_mgt";
429
516
 			};
430
517
 		};
431
518
 		i2c@4 {
..
..
@@ -539,6 +626,7 @@
539
626
 /* ULPI SMSC USB3320 */
540
627
 &usb0 {
541
628
 	status = "okay";
629
+	dr_mode = "host";
542
630
 };
543
631
 
544
632
 &watchdog0 {