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2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/arch/arm64/boot/dts/rockchip/rk3368.dtsi
....@@ -8,16 +8,8 @@
88 #include <dt-bindings/interrupt-controller/irq.h>
99 #include <dt-bindings/interrupt-controller/arm-gic.h>
1010 #include <dt-bindings/pinctrl/rockchip.h>
11
-#include <dt-bindings/power/rk3368-power.h>
1211 #include <dt-bindings/soc/rockchip,boot-mode.h>
13
-#include <dt-bindings/soc/rockchip-system-status.h>
14
-#include <dt-bindings/suspend/rockchip-rk3368.h>
1512 #include <dt-bindings/thermal/thermal.h>
16
-#include <dt-bindings/display/mipi_dsi.h>
17
-#include <dt-bindings/display/drm_mipi_dsi.h>
18
-#include <dt-bindings/display/media-bus-format.h>
19
-
20
-#include "rk3368-dram-default-timing.dtsi"
2113 
2214 / {
2315 	compatible = "rockchip,rk3368";
....@@ -27,15 +19,16 @@
2719 
2820 	aliases {
2921 		ethernet0 = &gmac;
22
+		gpio0 = &gpio0;
23
+		gpio1 = &gpio1;
24
+		gpio2 = &gpio2;
25
+		gpio3 = &gpio3;
3026 		i2c0 = &i2c0;
3127 		i2c1 = &i2c1;
3228 		i2c2 = &i2c2;
3329 		i2c3 = &i2c3;
3430 		i2c4 = &i2c4;
3531 		i2c5 = &i2c5;
36
-		mmc0 = &sdmmc;
37
-		mmc1 = &sdio0;
38
-		mmc2 = &emmc;
3932 		serial0 = &uart0;
4033 		serial1 = &uart1;
4134 		serial2 = &uart2;
....@@ -53,21 +46,6 @@
5346 		cpu-map {
5447 			cluster0 {
5548 				core0 {
56
-					cpu = <&cpu_l0>;
57
-				};
58
-				core1 {
59
-					cpu = <&cpu_l1>;
60
-				};
61
-				core2 {
62
-					cpu = <&cpu_l2>;
63
-				};
64
-				core3 {
65
-					cpu = <&cpu_l3>;
66
-				};
67
-			};
68
-
69
-			cluster1 {
70
-				core0 {
7149 					cpu = <&cpu_b0>;
7250 				};
7351 				core1 {
....@@ -80,333 +58,89 @@
8058 					cpu = <&cpu_b3>;
8159 				};
8260 			};
61
+
62
+			cluster1 {
63
+				core0 {
64
+					cpu = <&cpu_l0>;
65
+				};
66
+				core1 {
67
+					cpu = <&cpu_l1>;
68
+				};
69
+				core2 {
70
+					cpu = <&cpu_l2>;
71
+				};
72
+				core3 {
73
+					cpu = <&cpu_l3>;
74
+				};
75
+			};
8376 		};
8477 
8578 		cpu_l0: cpu@0 {
8679 			device_type = "cpu";
87
-			compatible = "arm,cortex-a53", "arm,armv8";
80
+			compatible = "arm,cortex-a53";
8881 			reg = <0x0 0x0>;
8982 			enable-method = "psci";
90
-			clocks = <&cru ARMCLKL>;
91
-			next-level-cache = <&cluster0_l2>;
92
-			operating-points-v2 = <&cluster0_opp>;
93
-			sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
9483 			#cooling-cells = <2>; /* min followed by max */
95
-			dynamic-power-coefficient = <149>;
9684 		};
9785 
9886 		cpu_l1: cpu@1 {
9987 			device_type = "cpu";
100
-			compatible = "arm,cortex-a53", "arm,armv8";
88
+			compatible = "arm,cortex-a53";
10189 			reg = <0x0 0x1>;
10290 			enable-method = "psci";
103
-			clocks = <&cru ARMCLKL>;
104
-			next-level-cache = <&cluster0_l2>;
105
-			operating-points-v2 = <&cluster0_opp>;
106
-			sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
91
+			#cooling-cells = <2>; /* min followed by max */
10792 		};
10893 
10994 		cpu_l2: cpu@2 {
11095 			device_type = "cpu";
111
-			compatible = "arm,cortex-a53", "arm,armv8";
96
+			compatible = "arm,cortex-a53";
11297 			reg = <0x0 0x2>;
11398 			enable-method = "psci";
114
-			clocks = <&cru ARMCLKL>;
115
-			next-level-cache = <&cluster0_l2>;
116
-			operating-points-v2 = <&cluster0_opp>;
117
-			sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
99
+			#cooling-cells = <2>; /* min followed by max */
118100 		};
119101 
120102 		cpu_l3: cpu@3 {
121103 			device_type = "cpu";
122
-			compatible = "arm,cortex-a53", "arm,armv8";
104
+			compatible = "arm,cortex-a53";
123105 			reg = <0x0 0x3>;
124106 			enable-method = "psci";
125
-			clocks = <&cru ARMCLKL>;
126
-			next-level-cache = <&cluster0_l2>;
127
-			operating-points-v2 = <&cluster0_opp>;
128
-			sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
107
+			#cooling-cells = <2>; /* min followed by max */
129108 		};
130109 
131110 		cpu_b0: cpu@100 {
132111 			device_type = "cpu";
133
-			compatible = "arm,cortex-a53", "arm,armv8";
112
+			compatible = "arm,cortex-a53";
134113 			reg = <0x0 0x100>;
135114 			enable-method = "psci";
136
-			clocks = <&cru ARMCLKB>;
137
-			next-level-cache = <&cluster1_l2>;
138
-			operating-points-v2 = <&cluster1_opp>;
139
-			sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
140115 			#cooling-cells = <2>; /* min followed by max */
141
-			dynamic-power-coefficient = <160>;
142116 		};
143117 
144118 		cpu_b1: cpu@101 {
145119 			device_type = "cpu";
146
-			compatible = "arm,cortex-a53", "arm,armv8";
120
+			compatible = "arm,cortex-a53";
147121 			reg = <0x0 0x101>;
148122 			enable-method = "psci";
149
-			clocks = <&cru ARMCLKB>;
150
-			next-level-cache = <&cluster1_l2>;
151
-			operating-points-v2 = <&cluster1_opp>;
152
-			sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
123
+			#cooling-cells = <2>; /* min followed by max */
153124 		};
154125 
155126 		cpu_b2: cpu@102 {
156127 			device_type = "cpu";
157
-			compatible = "arm,cortex-a53", "arm,armv8";
128
+			compatible = "arm,cortex-a53";
158129 			reg = <0x0 0x102>;
159130 			enable-method = "psci";
160
-			clocks = <&cru ARMCLKB>;
161
-			next-level-cache = <&cluster1_l2>;
162
-			operating-points-v2 = <&cluster1_opp>;
163
-			sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
131
+			#cooling-cells = <2>; /* min followed by max */
164132 		};
165133 
166134 		cpu_b3: cpu@103 {
167135 			device_type = "cpu";
168
-			compatible = "arm,cortex-a53", "arm,armv8";
136
+			compatible = "arm,cortex-a53";
169137 			reg = <0x0 0x103>;
170138 			enable-method = "psci";
171
-			clocks = <&cru ARMCLKB>;
172
-			next-level-cache = <&cluster1_l2>;
173
-			operating-points-v2 = <&cluster1_opp>;
174
-			sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
175
-		};
176
-
177
-		cluster0_l2: l2-cache0 {
178
-			compatible = "cache";
179
-		};
180
-
181
-		cluster1_l2: l2-cache1 {
182
-			compatible = "cache";
139
+			#cooling-cells = <2>; /* min followed by max */
183140 		};
184141 	};
185142 
186
-	cluster0_opp: opp_table0 {
187
-		compatible = "operating-points-v2";
188
-		opp-shared;
189
-		rockchip,leakage-voltage-sel = <
190
-			1   24   0
191
-			25  254  1
192
-		>;
193
-		nvmem-cells = <&cpu_leakage>, <&leakage_temp>, <&leakage_volt>;
194
-		nvmem-cell-names = "cpu_leakage", "leakage_temp",
195
-				   "leakage_volt";
196
-		rockchip,reboot-freq = <816000>;
197
-
198
-		opp-216000000 {
199
-			opp-hz = /bits/ 64 <216000000>;
200
-			opp-microvolt = <950000 950000 1350000>;
201
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
202
-			opp-microvolt-L1 = <950000 950000 1350000>;
203
-			clock-latency-ns = <40000>;
204
-			opp-suspend;
205
-		};
206
-		opp-408000000 {
207
-			opp-hz = /bits/ 64 <408000000>;
208
-			opp-microvolt = <950000 950000 1350000>;
209
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
210
-			opp-microvolt-L1 = <950000 950000 1350000>;
211
-			clock-latency-ns = <40000>;
212
-		};
213
-		opp-600000000 {
214
-			opp-hz = /bits/ 64 <600000000>;
215
-			opp-microvolt = <950000 950000 1350000>;
216
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
217
-			opp-microvolt-L1 = <950000 950000 1350000>;
218
-			clock-latency-ns = <40000>;
219
-		};
220
-		opp-816000000 {
221
-			opp-hz = /bits/ 64 <816000000>;
222
-			opp-microvolt = <1025000 1025000 1350000>;
223
-			opp-microvolt-L0 = <1125000 1125000 1350000>;
224
-			opp-microvolt-L1 = <1025000 1025000 1350000>;
225
-			clock-latency-ns = <40000>;
226
-		};
227
-		opp-1008000000 {
228
-			opp-hz = /bits/ 64 <1008000000>;
229
-			opp-microvolt = <1125000 1125000 1350000>;
230
-			opp-microvolt-L0 = <1225000 1225000 1350000>;
231
-			opp-microvolt-L1 = <1125000 1125000 1350000>;
232
-			clock-latency-ns = <40000>;
233
-		};
234
-		opp-1200000000 {
235
-			opp-hz = /bits/ 64 <1200000000>;
236
-			opp-microvolt = <1225000 1225000 1350000>;
237
-			opp-microvolt-L0 = <1325000 1325000 1350000>;
238
-			opp-microvolt-L1 = <1225000 1225000 1350000>;
239
-			clock-latency-ns = <40000>;
240
-		};
241
-	};
242
-
243
-	cluster1_opp: opp_table1 {
244
-		compatible = "operating-points-v2";
245
-		opp-shared;
246
-		rockchip,avs-sclae = <36>;
247
-		rockchip,leakage-scaling-sel = <
248
-			1   24   36
249
-			25  254  0
250
-		>;
251
-		clocks = <&cru PLL_APLLB>;
252
-		rockchip,leakage-voltage-sel = <
253
-			1   24   0
254
-			25  50   1
255
-			51  254  2
256
-		>;
257
-		nvmem-cells = <&cpu_leakage>, <&leakage_temp>, <&leakage_volt>;
258
-		nvmem-cell-names = "cpu_leakage", "leakage_temp",
259
-				   "leakage_volt";
260
-		rockchip,reboot-freq = <816000>;
261
-
262
-		opp-216000000 {
263
-			opp-hz = /bits/ 64 <216000000>;
264
-			opp-microvolt = <950000 950000 1350000>;
265
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
266
-			opp-microvolt-L1 = <950000 950000 1350000>;
267
-			opp-microvolt-L2 = <950000 950000 1350000>;
268
-			clock-latency-ns = <40000>;
269
-			opp-suspend;
270
-		};
271
-		opp-408000000 {
272
-			opp-hz = /bits/ 64 <408000000>;
273
-			opp-microvolt = <950000 950000 1350000>;
274
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
275
-			opp-microvolt-L1 = <950000 950000 1350000>;
276
-			opp-microvolt-L2 = <950000 950000 1350000>;
277
-			clock-latency-ns = <40000>;
278
-		};
279
-		opp-600000000 {
280
-			opp-hz = /bits/ 64 <600000000>;
281
-			opp-microvolt = <950000 950000 1350000>;
282
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
283
-			opp-microvolt-L1 = <950000 950000 1350000>;
284
-			opp-microvolt-L2 = <950000 950000 1350000>;
285
-			clock-latency-ns = <40000>;
286
-		};
287
-		opp-816000000 {
288
-			opp-hz = /bits/ 64 <816000000>;
289
-			opp-microvolt = <975000 975000 1350000>;
290
-			opp-microvolt-L0 = <1075000 1075000 1350000>;
291
-			opp-microvolt-L1 = <975000 975000 1350000>;
292
-			opp-microvolt-L2 = <975000 975000 1350000>;
293
-			clock-latency-ns = <40000>;
294
-		};
295
-		opp-1008000000 {
296
-			opp-hz = /bits/ 64 <1008000000>;
297
-			opp-microvolt = <1050000 1050000 1350000>;
298
-			opp-microvolt-L0 = <1150000 1150000 1350000>;
299
-			opp-microvolt-L1 = <1050000 1050000 1350000>;
300
-			opp-microvolt-L2 = <1025000 1025000 1350000>;
301
-			clock-latency-ns = <40000>;
302
-		};
303
-		opp-1200000000 {
304
-			opp-hz = /bits/ 64 <1200000000>;
305
-			opp-microvolt = <1150000 1150000 1350000>;
306
-			opp-microvolt-L0 = <1250000 1250000 1350000>;
307
-			opp-microvolt-L1 = <1150000 1150000 1350000>;
308
-			opp-microvolt-L2 = <1125000 1125000 1350000>;
309
-			clock-latency-ns = <40000>;
310
-		};
311
-		opp-1296000000 {
312
-			opp-hz = /bits/ 64 <1296000000>;
313
-			opp-microvolt = <1225000 1225000 1350000>;
314
-			opp-microvolt-L0 = <1350000 1350000 1350000>;
315
-			opp-microvolt-L1 = <1225000 1225000 1350000>;
316
-			opp-microvolt-L2 = <1200000 1200000 1350000>;
317
-			clock-latency-ns = <40000>;
318
-		};
319
-		opp-1416000000 {
320
-			opp-hz = /bits/ 64 <1416000000>;
321
-			opp-microvolt = <1300000 1300000 1350000>;
322
-			opp-microvolt-L0 = <1350000 1350000 1350000>;
323
-			opp-microvolt-L1 = <1300000 1300000 1350000>;
324
-			opp-microvolt-L2 = <1275000 1275000 1350000>;
325
-			clock-latency-ns = <40000>;
326
-		};
327
-		opp-1512000000 {
328
-			opp-hz = /bits/ 64 <1512000000>;
329
-			opp-microvolt = <1350000 1350000 1350000>;
330
-			opp-microvolt-L0 = <1350000 1350000 1350000>;
331
-			opp-microvolt-L1 = <1350000 1350000 1350000>;
332
-			opp-microvolt-L2 = <1325000 1325000 1350000>;
333
-			clock-latency-ns = <40000>;
334
-		};
335
-	};
336
-
337
-	energy-costs {
338
-		RK3368_CPU_COST_0: rk3368-core-cost0 {
339
-			busy-cost-data = <
340
-				146    44	/*  216M */
341
-				276    72	/*  408M */
342
-				406    99	/*  600M */
343
-				552    147	/*  816M */
344
-				682    200	/* 1008M */
345
-				812    255	/* 1200M */
346
-			>;
347
-			idle-cost-data = <
348
-				  6
349
-				  6
350
-				  0
351
-			>;
352
-		};
353
-
354
-		RK3368_CPU_COST_1: rk3368-core-cost1 {
355
-			busy-cost-data = <
356
-				146    53	/*  216M */
357
-				276    86	/*  408M */
358
-				406    118	/*  600M */
359
-				552    166	/*  816M */
360
-				682    226	/* 1008M */
361
-				812    309	/* 1200M */
362
-				878    371	/* 1200M */
363
-				959    446	/* 1416M */
364
-				1024   513	/* 1512M */
365
-			>;
366
-			idle-cost-data = <
367
-				   6
368
-				   6
369
-				   0
370
-			>;
371
-		};
372
-
373
-		RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
374
-			busy-cost-data = <
375
-				146    9	/*  216M */
376
-				276    14	/*  408M */
377
-				406    20	/*  600M */
378
-				552    29	/*  816M */
379
-				682    40	/* 1008M */
380
-				812    51	/* 1200M */
381
-			>;
382
-			idle-cost-data = <
383
-				56
384
-				56
385
-				56
386
-			>;
387
-		};
388
-
389
-		RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
390
-			busy-cost-data = <
391
-				146    11	/*  216M */
392
-				276    17	/*  408M */
393
-				406    24	/*  600M */
394
-				552    33	/*  816M */
395
-				682    45	/* 1008M */
396
-				812    62	/* 1200M */
397
-				878    74	/* 1200M */
398
-				959    89	/* 1416M */
399
-				1024   103	/* 1512M */
400
-			>;
401
-			idle-cost-data = <
402
-				56
403
-				56
404
-				56
405
-			>;
406
-		};
407
-	};
408
-
409
-	amba {
143
+	amba: bus {
410144 		compatible = "simple-bus";
411145 		#address-cells = <2>;
412146 		#size-cells = <2>;
....@@ -452,13 +186,6 @@
452186 				     <&cpu_b2>, <&cpu_b3>;
453187 	};
454188 
455
-	firmware {
456
-		optee: optee {
457
-			compatible = "linaro,optee-tz";
458
-			method = "smc";
459
-		};
460
-	};
461
-
462189 	psci {
463190 		compatible = "arm,psci-0.2";
464191 		method = "smc";
....@@ -483,7 +210,7 @@
483210 		#clock-cells = <0>;
484211 	};
485212 
486
-	sdmmc: dwmmc@ff0c0000 {
213
+	sdmmc: mmc@ff0c0000 {
487214 		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
488215 		reg = <0x0 0xff0c0000 0x0 0x4000>;
489216 		max-frequency = <150000000>;
....@@ -497,7 +224,7 @@
497224 		status = "disabled";
498225 	};
499226 
500
-	sdio0: dwmmc@ff0d0000 {
227
+	sdio0: mmc@ff0d0000 {
501228 		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
502229 		reg = <0x0 0xff0d0000 0x0 0x4000>;
503230 		max-frequency = <150000000>;
....@@ -511,7 +238,7 @@
511238 		status = "disabled";
512239 	};
513240 
514
-	emmc: dwmmc@ff0f0000 {
241
+	emmc: mmc@ff0f0000 {
515242 		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
516243 		reg = <0x0 0xff0f0000 0x0 0x4000>;
517244 		max-frequency = <150000000>;
....@@ -571,19 +298,6 @@
571298 		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
572299 		pinctrl-names = "default";
573300 		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
574
-		#address-cells = <1>;
575
-		#size-cells = <0>;
576
-		status = "disabled";
577
-	};
578
-
579
-	i2c0: i2c@ff650000 {
580
-		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
581
-		reg = <0x0 0xff650000 0x0 0x1000>;
582
-		clocks = <&cru PCLK_I2C0>;
583
-		clock-names = "i2c";
584
-		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
585
-		pinctrl-names = "default";
586
-		pinctrl-0 = <&i2c0_xfer>;
587301 		#address-cells = <1>;
588302 		#size-cells = <0>;
589303 		status = "disabled";
....@@ -689,25 +403,64 @@
689403 		status = "disabled";
690404 	};
691405 
692
-	thermal_zones: thermal-zones {
693
-		soc_thermal: soc-thermal {
694
-			polling-delay-passive = <200>; /* milliseconds */
695
-			polling-delay = <200>; /* milliseconds */
696
-			sustainable-power = <600>; /* milliwatts */
406
+	thermal-zones {
407
+		cpu {
408
+			polling-delay-passive = <100>; /* milliseconds */
409
+			polling-delay = <5000>; /* milliseconds */
697410 
698411 			thermal-sensors = <&tsadc 0>;
412
+
699413 			trips {
700
-				threshold: trip-point-0 {
701
-					temperature = <70000>; /* millicelsius */
414
+				cpu_alert0: cpu_alert0 {
415
+					temperature = <75000>; /* millicelsius */
702416 					hysteresis = <2000>; /* millicelsius */
703417 					type = "passive";
704418 				};
705
-				target: trip-point-1 {
419
+				cpu_alert1: cpu_alert1 {
706420 					temperature = <80000>; /* millicelsius */
707421 					hysteresis = <2000>; /* millicelsius */
708422 					type = "passive";
709423 				};
710
-				soc_crit: soc-crit {
424
+				cpu_crit: cpu_crit {
425
+					temperature = <95000>; /* millicelsius */
426
+					hysteresis = <2000>; /* millicelsius */
427
+					type = "critical";
428
+				};
429
+			};
430
+
431
+			cooling-maps {
432
+				map0 {
433
+					trip = <&cpu_alert0>;
434
+					cooling-device =
435
+					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
436
+					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
437
+					<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
438
+					<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
439
+				};
440
+				map1 {
441
+					trip = <&cpu_alert1>;
442
+					cooling-device =
443
+					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
444
+					<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
445
+					<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
446
+					<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
447
+				};
448
+			};
449
+		};
450
+
451
+		gpu {
452
+			polling-delay-passive = <100>; /* milliseconds */
453
+			polling-delay = <5000>; /* milliseconds */
454
+
455
+			thermal-sensors = <&tsadc 1>;
456
+
457
+			trips {
458
+				gpu_alert0: gpu_alert0 {
459
+					temperature = <80000>; /* millicelsius */
460
+					hysteresis = <2000>; /* millicelsius */
461
+					type = "passive";
462
+				};
463
+				gpu_crit: gpu_crit {
711464 					temperature = <115000>; /* millicelsius */
712465 					hysteresis = <2000>; /* millicelsius */
713466 					type = "critical";
....@@ -716,46 +469,31 @@
716469 
717470 			cooling-maps {
718471 				map0 {
719
-					trip = <&target>;
472
+					trip = <&gpu_alert0>;
720473 					cooling-device =
721
-					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
722
-					contribution = <1024>;
723
-				};
724
-				map1 {
725
-					trip = <&target>;
726
-					cooling-device =
727
-					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
728
-					contribution = <1024>;
729
-				};
730
-				map2 {
731
-					trip = <&target>;
732
-					cooling-device =
733
-					<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
734
-					contribution = <1024>;
474
+					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
475
+					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
476
+					<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477
+					<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
735478 				};
736479 			};
737
-		};
738
-
739
-		gpu_thermal: gpu-thermal {
740
-			polling-delay-passive = <200>; /* milliseconds */
741
-			polling-delay = <200>; /* milliseconds */
742
-			thermal-sensors = <&tsadc 1>;
743480 		};
744481 	};
745482 
746483 	tsadc: tsadc@ff280000 {
747
-		compatible = "rockchip,rk3368-tsadc-legacy";
484
+		compatible = "rockchip,rk3368-tsadc";
748485 		reg = <0x0 0xff280000 0x0 0x100>;
749486 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
750487 		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
751488 		clock-names = "tsadc", "apb_pclk";
752
-		clock-frequency = <32768>;
753489 		resets = <&cru SRST_TSADC>;
754490 		reset-names = "tsadc-apb";
755
-		nvmem-cells = <&temp_adjust>;
756
-		nvmem-cell-names = "temp_adjust";
491
+		pinctrl-names = "init", "default", "sleep";
492
+		pinctrl-0 = <&otp_pin>;
493
+		pinctrl-1 = <&otp_out>;
494
+		pinctrl-2 = <&otp_pin>;
757495 		#thermal-sensor-cells = <1>;
758
-		hw-shut-temp = <95000>;
496
+		rockchip,hw-tshut-temp = <95000>;
759497 		status = "disabled";
760498 	};
761499 
....@@ -776,35 +514,11 @@
776514 		status = "disabled";
777515 	};
778516 
779
-	nandc0: nandc@ff400000 {
780
-		compatible = "rockchip,rk-nandc";
781
-		reg = <0x0 0xff400000 0x0 0x4000>;
782
-		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
783
-		nandc_id = <0>;
784
-		clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
785
-		clock-names = "clk_nandc", "hclk_nandc";
786
-		status = "disabled";
787
-	};
788
-
789517 	usb_host0_ehci: usb@ff500000 {
790518 		compatible = "generic-ehci";
791
-		reg = <0x0 0xff500000 0x0 0x20000>;
519
+		reg = <0x0 0xff500000 0x0 0x100>;
792520 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
793
-		clocks = <&cru HCLK_HOST0>, <&u2phy>;
794
-		clock-names = "usbhost", "utmi";
795
-		phys = <&u2phy_host>;
796
-		phy-names = "usb";
797
-		status = "disabled";
798
-	};
799
-
800
-	usb_host0_ohci: usb@ff520000 {
801
-		compatible = "generic-ohci";
802
-		reg = <0x0 0xff520000 0x0 0x20000>;
803
-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
804
-		clocks = <&cru HCLK_HOST0>, <&u2phy>;
805
-		clock-names = "usbhost", "utmi";
806
-		phys = <&u2phy_host>;
807
-		phy-names = "usb";
521
+		clocks = <&cru HCLK_HOST0>;
808522 		status = "disabled";
809523 	};
810524 
....@@ -817,17 +531,22 @@
817531 		clock-names = "otg";
818532 		dr_mode = "otg";
819533 		g-np-tx-fifo-size = <16>;
820
-		g-rx-fifo-size = <280>;
821
-		g-tx-fifo-size = <256 128 128 64 32 16>;
822
-		g-use-dma;
823
-		phys = <&u2phy_otg>;
824
-		phy-names = "usb2-phy";
534
+		g-rx-fifo-size = <275>;
535
+		g-tx-fifo-size = <256 128 128 64 64 32>;
825536 		status = "disabled";
826537 	};
827538 
828
-	ddrpctl: syscon@ff610000 {
829
-		compatible = "rockchip,rk3368-ddrpctl", "syscon";
830
-		reg = <0x0 0xff610000 0x0 0x400>;
539
+	i2c0: i2c@ff650000 {
540
+		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
541
+		reg = <0x0 0xff650000 0x0 0x1000>;
542
+		clocks = <&cru PCLK_I2C0>;
543
+		clock-names = "i2c";
544
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
545
+		pinctrl-names = "default";
546
+		pinctrl-0 = <&i2c0_xfer>;
547
+		#address-cells = <1>;
548
+		#size-cells = <0>;
549
+		status = "disabled";
831550 	};
832551 
833552 	i2c1: i2c@ff660000 {
....@@ -911,196 +630,6 @@
911630 		status = "disabled";
912631 	};
913632 
914
-	mailbox: mailbox@ff6b0000 {
915
-		compatible = "rockchip,rk3368-mbox-legacy";
916
-		reg = <0x0 0xff6b0000 0x0 0x1000>,
917
-		      <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
918
-		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
919
-			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
920
-			     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
921
-			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
922
-		clocks = <&cru PCLK_MAILBOX>;
923
-		clock-names = "pclk_mailbox";
924
-		#mbox-cells = <1>;
925
-		status = "disabled";
926
-	};
927
-
928
-	mailbox_scpi: mailbox-scpi {
929
-		compatible = "rockchip,rk3368-scpi-legacy";
930
-		mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
931
-		chan-nums = <3>;
932
-		status = "disabled";
933
-	};
934
-
935
-	qos_iep: qos@ffad0000 {
936
-		compatible = "syscon";
937
-		reg = <0x0 0xffad0000 0x0 0x20>;
938
-	};
939
-
940
-	qos_isp_r0: qos@ffad0080 {
941
-		compatible = "syscon";
942
-		reg = <0x0 0xffad0080 0x0 0x20>;
943
-	};
944
-
945
-	qos_isp_r1: qos@ffad0100 {
946
-		compatible = "syscon";
947
-		reg = <0x0 0xffad0100 0x0 0x20>;
948
-	};
949
-
950
-	qos_isp_w0: qos@ffad0180 {
951
-		compatible = "syscon";
952
-		reg = <0x0 0xffad0180 0x0 0x20>;
953
-	};
954
-
955
-	qos_isp_w1: qos@ffad0200 {
956
-		compatible = "syscon";
957
-		reg = <0x0 0xffad0200 0x0 0x20>;
958
-	};
959
-
960
-	qos_vip: qos@ffad0280 {
961
-		compatible = "syscon";
962
-		reg = <0x0 0xffad0280 0x0 0x20>;
963
-	};
964
-
965
-	qos_vop: qos@ffad0300 {
966
-		compatible = "syscon";
967
-		reg = <0x0 0xffad0300 0x0 0x20>;
968
-	};
969
-
970
-	qos_rga_r: qos@ffad0380 {
971
-		compatible = "syscon";
972
-		reg = <0x0 0xffad0380 0x0 0x20>;
973
-	};
974
-
975
-	qos_rga_w: qos@ffad0400 {
976
-		compatible = "syscon";
977
-		reg = <0x0 0xffad0400 0x0 0x20>;
978
-	};
979
-
980
-	qos_hevc_r: qos@ffae0000 {
981
-		compatible = "syscon";
982
-		reg = <0x0 0xffae0000 0x0 0x20>;
983
-	};
984
-
985
-	qos_vpu_r: qos@ffae0100 {
986
-		compatible = "syscon";
987
-		reg = <0x0 0xffae0100 0x0 0x20>;
988
-	};
989
-
990
-	qos_vpu_w: qos@ffae0180 {
991
-		compatible = "syscon";
992
-		reg = <0x0 0xffae0180 0x0 0x20>;
993
-	};
994
-
995
-	qos_gpu: qos@ffaf0000 {
996
-		compatible = "syscon";
997
-		reg = <0x0 0xffaf0000 0x0 0x20>;
998
-	};
999
-
1000
-	pmu: power-management@ff730000 {
1001
-		compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
1002
-		reg = <0x0 0xff730000 0x0 0x1000>;
1003
-
1004
-		power: power-controller {
1005
-			compatible = "rockchip,rk3368-power-controller";
1006
-			#power-domain-cells = <1>;
1007
-			#address-cells = <1>;
1008
-			#size-cells = <0>;
1009
-
1010
-			/*
1011
-			 * Note: Although SCLK_* are the working clocks
1012
-			 * of device without including on the NOC, needed for
1013
-			 * synchronous reset.
1014
-			 *
1015
-			 * The clocks on the which NOC:
1016
-			 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1017
-			 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1018
-			 * ACLK_RGA is on ACLK_RGA_NIU.
1019
-			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1020
-			 *
1021
-			 * Which clock are device clocks:
1022
-			 *	clocks		devices
1023
-			 *	*_IEP		IEP:Image Enhancement Processor
1024
-			 *	*_ISP		ISP:Image Signal Processing
1025
-			 *	*_VIP		VIP:Video Input Processor
1026
-			 *	*_VOP*		VOP:Visual Output Processor
1027
-			 *	*_RGA		RGA
1028
-			 *	*_EDP*		EDP
1029
-			 *	*_DPHY*		LVDS
1030
-			 *	*_HDMI		HDMI
1031
-			 *	*_MIPI_*	MIPI
1032
-			 */
1033
-			pd_vio@RK3368_PD_VIO {
1034
-				reg = <RK3368_PD_VIO>;
1035
-				clocks = <&cru ACLK_IEP>,
1036
-					 <&cru ACLK_ISP>,
1037
-					 <&cru ACLK_VIP>,
1038
-					 <&cru ACLK_RGA>,
1039
-					 <&cru ACLK_VOP>,
1040
-					 <&cru ACLK_VOP_IEP>,
1041
-					 <&cru DCLK_VOP>,
1042
-					 <&cru HCLK_IEP>,
1043
-					 <&cru HCLK_ISP>,
1044
-					 <&cru HCLK_RGA>,
1045
-					 <&cru HCLK_VIP>,
1046
-					 <&cru HCLK_VOP>,
1047
-					 <&cru HCLK_VIO_HDCPMMU>,
1048
-					 <&cru PCLK_EDP_CTRL>,
1049
-					 <&cru PCLK_HDMI_CTRL>,
1050
-					 <&cru PCLK_HDCP>,
1051
-					 <&cru PCLK_ISP>,
1052
-					 <&cru PCLK_VIP>,
1053
-					 <&cru PCLK_DPHYRX>,
1054
-					 <&cru PCLK_DPHYTX0>,
1055
-					 <&cru PCLK_MIPI_CSI>,
1056
-					 <&cru PCLK_MIPI_DSI0>,
1057
-					 <&cru SCLK_VOP0_PWM>,
1058
-					 <&cru SCLK_EDP_24M>,
1059
-					 <&cru SCLK_EDP>,
1060
-					 <&cru SCLK_HDCP>,
1061
-					 <&cru SCLK_ISP>,
1062
-					 <&cru SCLK_RGA>,
1063
-					 <&cru SCLK_HDMI_CEC>,
1064
-					 <&cru SCLK_HDMI_HDCP>;
1065
-				pm_qos = <&qos_iep>,
1066
-					 <&qos_isp_r0>,
1067
-					 <&qos_isp_r1>,
1068
-					 <&qos_isp_w0>,
1069
-					 <&qos_isp_w1>,
1070
-					 <&qos_vip>,
1071
-					 <&qos_vop>,
1072
-					 <&qos_rga_r>,
1073
-					 <&qos_rga_w>;
1074
-			};
1075
-			/*
1076
-			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1077
-			 * (video endecoder & decoder) clocks that on the
1078
-			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1079
-			 */
1080
-			pd_video@RK3368_PD_VIDEO {
1081
-				reg = <RK3368_PD_VIDEO>;
1082
-				clocks = <&cru ACLK_VIDEO>,
1083
-					 <&cru HCLK_VIDEO>,
1084
-					 <&cru SCLK_HEVC_CABAC>,
1085
-					 <&cru SCLK_HEVC_CORE>;
1086
-				pm_qos = <&qos_hevc_r>,
1087
-					 <&qos_vpu_r>,
1088
-					 <&qos_vpu_w>;
1089
-			};
1090
-			/*
1091
-			 * Note: ACLK_GPU is the GPU clock,
1092
-			 * and on the ACLK_GPU_NIU (NOC).
1093
-			 */
1094
-			pd_gpu_1@RK3368_PD_GPU_1 {
1095
-				reg = <RK3368_PD_GPU_1>;
1096
-				clocks = <&cru ACLK_GPU_CFG>,
1097
-					 <&cru ACLK_GPU_MEM>,
1098
-					 <&cru SCLK_GPU_CORE>;
1099
-				pm_qos = <&qos_gpu>;
1100
-			};
1101
-		};
1102
-	};
1103
-
1104633 	pmugrf: syscon@ff738000 {
1105634 		compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1106635 		reg = <0x0 0xff738000 0x0 0x1000>;
....@@ -1110,16 +639,7 @@
1110639 			status = "disabled";
1111640 		};
1112641 
1113
-		pvtm_clock: pvtm-clock {
1114
-			compatible = "rockchip,rk3368-pvtm-clock";
1115
-			#clock-cells = <0>;
1116
-			clocks = <&cru SCLK_PVTM_PMU>;
1117
-			clock-names = "pvtm_pmu_clk";
1118
-			clock-output-names = "xin32k_pvtm";
1119
-			status = "okay";
1120
-		};
1121
-
1122
-		reboot_mode: reboot-mode {
642
+		reboot-mode {
1123643 			compatible = "syscon-reboot-mode";
1124644 			offset = <0x200>;
1125645 			mode-normal = <BOOT_NORMAL>;
....@@ -1135,167 +655,15 @@
1135655 		rockchip,grf = <&grf>;
1136656 		#clock-cells = <1>;
1137657 		#reset-cells = <1>;
1138
-		assigned-clocks =
1139
-			<&cru ARMCLKL>, <&cru ARMCLKB>,
1140
-			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
1141
-			<&cru ACLK_BUS>, <&cru ACLK_PERI>,
1142
-			<&cru HCLK_BUS>, <&cru HCLK_PERI>,
1143
-			<&cru PCLK_BUS>, <&cru PCLK_PERI>,
1144
-			<&cru ACLK_CCI_PRE>;
1145
-		assigned-clock-rates =
1146
-			<600000000>, <600000000>,
1147
-			<576000000>, <400000000>,
1148
-			<300000000>, <300000000>,
1149
-			<150000000>, <150000000>,
1150
-			<75000000>, <75000000>,
1151
-			<576000000>;
1152658 	};
1153659 
1154660 	grf: syscon@ff770000 {
1155661 		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1156662 		reg = <0x0 0xff770000 0x0 0x1000>;
1157
-		#address-cells = <1>;
1158
-		#size-cells = <1>;
1159663 
1160664 		io_domains: io-domains {
1161665 			compatible = "rockchip,rk3368-io-voltage-domain";
1162666 			status = "disabled";
1163
-		};
1164
-
1165
-		lvds: lvds {
1166
-			compatible = "rockchip,rk3368-lvds";
1167
-			phys = <&video_phy>;
1168
-			phy-names = "phy";
1169
-			status = "disabled";
1170
-
1171
-			ports {
1172
-				#address-cells = <1>;
1173
-				#size-cells = <0>;
1174
-
1175
-				port@0 {
1176
-					reg = <0>;
1177
-
1178
-					lvds_in_vop: endpoint {
1179
-						remote-endpoint = <&vop_out_lvds>;
1180
-					};
1181
-				};
1182
-			};
1183
-		};
1184
-
1185
-		rgb: rgb {
1186
-			compatible = "rockchip,rk3368-rgb";
1187
-			phys = <&video_phy>;
1188
-			phy-names = "phy";
1189
-			pinctrl-names = "default", "sleep";
1190
-			pinctrl-0 = <&lcdc_rgb_pins>;
1191
-			pinctrl-1 = <&lcdc_sleep_pins>;
1192
-			status = "disabled";
1193
-
1194
-			ports {
1195
-				#address-cells = <1>;
1196
-				#size-cells = <0>;
1197
-
1198
-				port@0 {
1199
-					reg = <0>;
1200
-
1201
-					rgb_in_vop: endpoint {
1202
-						remote-endpoint = <&vop_out_rgb>;
1203
-					};
1204
-				};
1205
-			};
1206
-		};
1207
-
1208
-		u2phy: usb2-phy@700 {
1209
-			compatible = "rockchip,rk3368-usb2phy";
1210
-			reg = <0x700 0x2c>;
1211
-			clocks = <&cru SCLK_OTGPHY0>;
1212
-			clock-names = "phyclk";
1213
-			#clock-cells = <0>;
1214
-			clock-output-names = "usbotg_out";
1215
-			assigned-clocks = <&cru SCLK_USBPHY480M>;
1216
-			assigned-clock-parents = <&u2phy>;
1217
-			status = "disabled";
1218
-
1219
-			u2phy_otg: otg-port {
1220
-				#phy-cells = <0>;
1221
-				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1222
-					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1223
-					     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1224
-				interrupt-names = "otg-bvalid", "otg-id",
1225
-						  "linestate";
1226
-				status = "disabled";
1227
-			};
1228
-
1229
-			u2phy_host: host-port {
1230
-				#phy-cells = <0>;
1231
-				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1232
-				interrupt-names = "linestate";
1233
-				status = "disabled";
1234
-			};
1235
-		};
1236
-
1237
-		dfi: dfi {
1238
-			compatible = "rockchip,rk3368-dfi";
1239
-			status = "disabled";
1240
-		};
1241
-	};
1242
-
1243
-	dmc: dmc {
1244
-		compatible = "rockchip,rk3368-dmc";
1245
-		devfreq-events = <&dfi>;
1246
-		clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_DDRPHY>,
1247
-			 <&cru PCLK_DDRUPCTL>;
1248
-		clock-names = "dmc_clk", "pclk_phy", "pclk_upctl";
1249
-		ddr_timing = <&ddr_timing>;
1250
-		upthreshold = <50>;
1251
-		downdifferential = <20>;
1252
-		operating-points-v2 = <&dmc_opp_table>;
1253
-		vop-dclk-mode = <0>;
1254
-		system-status-freq = <
1255
-			/*system status		freq(KHz)*/
1256
-			SYS_STATUS_NORMAL	600000
1257
-			SYS_STATUS_REBOOT	600000
1258
-			SYS_STATUS_SUSPEND	192000
1259
-			SYS_STATUS_VIDEO_1080P	300000
1260
-			SYS_STATUS_VIDEO_4K	600000
1261
-			SYS_STATUS_PERFORMANCE	600000
1262
-			SYS_STATUS_BOOST	396000
1263
-			SYS_STATUS_DUALVIEW	600000
1264
-			SYS_STATUS_ISP		528000
1265
-		>;
1266
-		auto-min-freq = <396000>;
1267
-		auto-freq-en = <0>;
1268
-		status = "disabled";
1269
-	};
1270
-
1271
-	dmc_opp_table: opp_table2 {
1272
-		compatible = "operating-points-v2";
1273
-
1274
-		opp-192000000 {
1275
-			opp-hz = /bits/ 64 <192000000>;
1276
-			opp-microvolt = <1100000>;
1277
-		};
1278
-
1279
-		opp-240000000 {
1280
-			opp-hz = /bits/ 64 <240000000>;
1281
-			opp-microvolt = <1100000>;
1282
-		};
1283
-
1284
-		opp-300000000 {
1285
-			opp-hz = /bits/ 64 <300000000>;
1286
-			opp-microvolt = <1100000>;
1287
-		};
1288
-		opp-396000000 {
1289
-			opp-hz = /bits/ 64 <396000000>;
1290
-			opp-microvolt = <1100000>;
1291
-		};
1292
-		opp-528000000 {
1293
-			opp-hz = /bits/ 64 <528000000>;
1294
-			opp-microvolt = <1100000>;
1295
-		};
1296
-		opp-600000000 {
1297
-			opp-hz = /bits/ 64 <600000000>;
1298
-			opp-microvolt = <1100000>;
1299667 		};
1300668 	};
1301669 
....@@ -1322,7 +690,7 @@
1322690 		dmas = <&dmac_bus 3>;
1323691 		dma-names = "tx";
1324692 		pinctrl-names = "default";
1325
-		pinctrl-0 = <&spdif_bus>;
693
+		pinctrl-0 = <&spdif_tx>;
1326694 		status = "disabled";
1327695 	};
1328696 
....@@ -1334,8 +702,6 @@
1334702 		clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1335703 		dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1336704 		dma-names = "tx", "rx";
1337
-		resets = <&cru SRST_I2S2CH>;
1338
-		reset-names = "reset-m";
1339705 		status = "disabled";
1340706 	};
1341707 
....@@ -1347,35 +713,8 @@
1347713 		clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1348714 		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1349715 		dma-names = "tx", "rx";
1350
-		resets = <&cru SRST_I2S8CH>;
1351
-		reset-names = "reset-m";
1352716 		pinctrl-names = "default";
1353717 		pinctrl-0 = <&i2s_8ch_bus>;
1354
-		status = "disabled";
1355
-	};
1356
-
1357
-	rng: rng@ff8a0000 {
1358
-		compatible = "rockchip,cryptov1-rng";
1359
-		reg = <0x0 0xff8a0000 0x0 0x4000>;
1360
-
1361
-		clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
1362
-		clock-names = "clk_crypto", "hclk_crypto";
1363
-		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
1364
-		assigned-clock-rates = <150000000>, <100000000>;
1365
-		status = "disabled";
1366
-	};
1367
-
1368
-	iep: iep@ff900000 {
1369
-		compatible = "rockchip,iep";
1370
-		iommu_enabled = <1>;
1371
-		iommus = <&iep_mmu>;
1372
-		reg = <0x0 0xff900000 0x0 0x800>;
1373
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1374
-		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1375
-		clock-names = "aclk_iep", "hclk_iep";
1376
-		power-domains = <&power RK3368_PD_VIO>;
1377
-		allocator = <1>;
1378
-		version = <2>;
1379718 		status = "disabled";
1380719 	};
1381720 
....@@ -1386,66 +725,7 @@
1386725 		interrupt-names = "iep_mmu";
1387726 		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1388727 		clock-names = "aclk", "iface";
1389
-		power-domains = <&power RK3368_PD_VIO>;
1390728 		#iommu-cells = <0>;
1391
-		status = "disabled";
1392
-	};
1393
-
1394
-	isp: isp@ff910000 {
1395
-		compatible = "rockchip,rk3368-isp", "rockchip,isp";
1396
-		reg = <0x0 0xff910000 0x0 0x4000>;
1397
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1398
-		power-domains = <&power RK3368_PD_VIO>;
1399
-		clocks =
1400
-			<&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1401
-			<&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1402
-			<&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1403
-			<&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1404
-		clock-names =
1405
-			"aclk_isp", "hclk_isp", "clk_isp",
1406
-			"clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1407
-			"clk_cif_pll", "hclk_mipiphy1",
1408
-			"pclk_dphyrx", "clk_vio0_noc";
1409
-
1410
-		pinctrl-names =
1411
-			"default", "isp_dvp8bit2", "isp_dvp10bit",
1412
-			"isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1413
-			"isp_mipi_fl", "isp_mipi_fl_prefl",
1414
-			"isp_flash_as_gpio", "isp_flash_as_trigger_out";
1415
-		pinctrl-0 = <&cif_clkout>;
1416
-		pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1417
-		pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1418
-		pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1419
-		pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1420
-		pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1421
-		pinctrl-6 = <&cif_clkout>;
1422
-		pinctrl-7 = <&cif_clkout &isp_prelight>;
1423
-		pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1424
-		pinctrl-9 = <&isp_flash_trigger>;
1425
-		rockchip,isp,mipiphy = <2>;
1426
-		rockchip,isp,cifphy = <1>;
1427
-		rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1428
-		rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1429
-		rockchip,grf = <&grf>;
1430
-		rockchip,cru = <&cru>;
1431
-		rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1432
-		rockchip,isp,iommu-enable = <1>;
1433
-		iommus = <&isp_mmu>;
1434
-		status = "disabled";
1435
-	};
1436
-
1437
-	rkisp1: rkisp1@ff910000 {
1438
-		compatible = "rockchip,rk3368-rkisp1";
1439
-		reg = <0x0 0xff910000 0x0 0x4000>;
1440
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1441
-		interrupt-names = "isp_irq";
1442
-		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1443
-			<&cru SCLK_ISP>, <&cru PCLK_ISP>;
1444
-		clock-names = "aclk_isp", "hclk_isp",
1445
-			"clk_isp", "pclk_isp";
1446
-		devfreq = <&dmc>;
1447
-		power-domains = <&power RK3368_PD_VIO>;
1448
-		iommus = <&isp_mmu>;
1449729 		status = "disabled";
1450730 	};
1451731 
....@@ -1458,62 +738,7 @@
1458738 		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1459739 		clock-names = "aclk", "iface";
1460740 		#iommu-cells = <0>;
1461
-		power-domains = <&power RK3368_PD_VIO>;
1462741 		rockchip,disable-mmu-reset;
1463
-		status = "disabled";
1464
-	};
1465
-
1466
-	vop: vop@ff930000 {
1467
-		compatible = "rockchip,rk3368-vop";
1468
-		rockchip,grf = <&grf>;
1469
-		reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
1470
-		reg-names = "regs", "gamma_lut";
1471
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1472
-		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1473
-		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1474
-		assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1475
-		assigned-clock-rates = <400000000>, <200000000>;
1476
-		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1477
-		reset-names = "axi", "ahb", "dclk";
1478
-		power-domains = <&power RK3368_PD_VIO>;
1479
-		iommus = <&vop_mmu>;
1480
-		status = "disabled";
1481
-
1482
-		vop_out: port {
1483
-			#address-cells = <1>;
1484
-			#size-cells = <0>;
1485
-
1486
-			vop_out_dsi: endpoint@0 {
1487
-				reg = <0>;
1488
-				remote-endpoint = <&dsi_in_vop>;
1489
-			};
1490
-
1491
-			vop_out_edp: endpoint@1 {
1492
-				reg = <1>;
1493
-				remote-endpoint = <&edp_in_vop>;
1494
-			};
1495
-
1496
-			vop_out_hdmi: endpoint@2 {
1497
-				reg = <2>;
1498
-				remote-endpoint = <&hdmi_in_vop>;
1499
-			};
1500
-
1501
-			vop_out_lvds: endpoint@3 {
1502
-				reg = <3>;
1503
-				remote-endpoint = <&lvds_in_vop>;
1504
-			};
1505
-
1506
-			vop_out_rgb: endpoint@4 {
1507
-				reg = <4>;
1508
-				remote-endpoint = <&rgb_in_vop>;
1509
-			};
1510
-		};
1511
-	};
1512
-
1513
-	display_subsystem: display-subsystem {
1514
-		compatible = "rockchip,display-subsystem";
1515
-		ports = <&vop_out>;
1516
-		devfreq = <&dmc>;
1517742 		status = "disabled";
1518743 	};
1519744 
....@@ -1524,229 +749,7 @@
1524749 		interrupt-names = "vop_mmu";
1525750 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1526751 		clock-names = "aclk", "iface";
1527
-		power-domains = <&power RK3368_PD_VIO>;
1528752 		#iommu-cells = <0>;
1529
-		status = "disabled";
1530
-	};
1531
-
1532
-	cif: cif@ff950000 {
1533
-		compatible = "rockchip,cif";
1534
-		reg = <0x0 0xff950000 0x0 0x400>;
1535
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1536
-		clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
1537
-				<&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
1538
-		clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
1539
-				"cif0_in", "cif0_out";
1540
-		resets = <&cru SRST_VIP>;
1541
-		reset-names = "rst_cif";
1542
-		pinctrl-names = "cif_pin_all";
1543
-		pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1544
-		rockchip,grf = <&grf>;
1545
-		power-domains = <&power RK3368_PD_VIO>;
1546
-		iommus = <&vip_mmu>;
1547
-		status = "disabled";
1548
-	};
1549
-
1550
-	cif_new: cif-new@ff950000 {
1551
-		compatible = "rockchip,rk3368-cif";
1552
-		reg = <0x0 0xff950000 0x0 0x400>;
1553
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1554
-		clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
1555
-				<&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
1556
-		clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
1557
-				"cif0_in", "cif0_out";
1558
-		resets = <&cru SRST_VIP>;
1559
-		reset-names = "rst_cif";
1560
-		rockchip,grf = <&grf>;
1561
-		power-domains = <&power RK3368_PD_VIO>;
1562
-		iommus = <&vip_mmu>;
1563
-		status = "disabled";
1564
-	};
1565
-
1566
-	vip_mmu: iommu@ff950800{
1567
-		compatible = "rockchip,iommu";
1568
-		reg = <0x0 0xff950800 0x0 0x100>;
1569
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1570
-		interrupt-names = "vip_mmu";
1571
-		clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>;
1572
-		clock-names = "aclk", "hclk";
1573
-		rk_iommu,disable_reset_quirk;
1574
-		#iommu-cells = <0>;
1575
-		power-domains = <&power RK3368_PD_VIO>;
1576
-		status = "disabled";
1577
-	};
1578
-
1579
-	dsi: dsi@ff960000 {
1580
-		compatible = "rockchip,rk3368-mipi-dsi";
1581
-		reg = <0x0 0xff960000 0x0 0x4000>;
1582
-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1583
-		clocks = <&cru PCLK_MIPI_DSI0>, <&video_phy>;
1584
-		clock-names = "pclk", "hs_clk";
1585
-		resets = <&cru SRST_MIPIDSI0>;
1586
-		reset-names = "apb";
1587
-		phys = <&video_phy>;
1588
-		phy-names = "mipi_dphy";
1589
-		rockchip,grf = <&grf>;
1590
-		power-domains = <&power RK3368_PD_VIO>;
1591
-		#address-cells = <1>;
1592
-		#size-cells = <0>;
1593
-		status = "disabled";
1594
-
1595
-		ports {
1596
-			port {
1597
-				dsi_in_vop: endpoint {
1598
-					remote-endpoint = <&vop_out_dsi>;
1599
-				};
1600
-			};
1601
-		};
1602
-	};
1603
-
1604
-	video_phy: video-phy@ff968000 {
1605
-		compatible = "rockchip,rk3368-video-phy";
1606
-		reg = <0x0 0xff968000 0x0 0x4000>,
1607
-		      <0x0 0xff960000 0x0 0x4000>;
1608
-		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
1609
-			 <&cru PCLK_MIPI_DSI0>;
1610
-		clock-names = "ref", "pclk_phy", "pclk_host";
1611
-		#clock-cells = <0>;
1612
-		resets = <&cru SRST_MIPIDPHYTX>;
1613
-		reset-names = "rst";
1614
-		power-domains = <&power RK3368_PD_VIO>;
1615
-		#phy-cells = <0>;
1616
-		status = "disabled";
1617
-	};
1618
-
1619
-	mipi_dphy_rx0: mipi-dphy-rx0@ff96C000 {
1620
-		compatible = "rockchip,rk3368-mipi-dphy";
1621
-		reg = <0x0 0xff96C000 0x0 0x4000>;
1622
-		clocks = <&cru PCLK_DPHYRX>;
1623
-		clock-names = "pclk_dphyrx";
1624
-		power-domains = <&power RK3368_PD_VIO>;
1625
-		rockchip,grf = <&grf>;
1626
-		status = "disabled";
1627
-	};
1628
-
1629
-	edp: edp@ff970000 {
1630
-		compatible = "rockchip,rk3368-edp";
1631
-		reg = <0x0 0xff970000 0x0 0x8000>;
1632
-		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1633
-		clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1634
-		clock-names = "dp", "pclk";
1635
-		assigned-clocks = <&cru SCLK_EDP_24M>;
1636
-		assigned-clock-parents = <&xin24m>;
1637
-		resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1638
-		reset-names = "dp", "apb";
1639
-		power-domains = <&power RK3368_PD_VIO>;
1640
-		rockchip,grf = <&grf>;
1641
-		status = "disabled";
1642
-
1643
-		ports {
1644
-			#address-cells = <1>;
1645
-			#size-cells = <0>;
1646
-
1647
-			port@0 {
1648
-				reg = <0>;
1649
-
1650
-				edp_in_vop: endpoint {
1651
-					remote-endpoint = <&vop_out_edp>;
1652
-				};
1653
-			};
1654
-		};
1655
-	};
1656
-
1657
-	hdmi: hdmi@ff980000 {
1658
-		compatible = "rockchip,rk3368-dw-hdmi";
1659
-		reg = <0x0 0xff980000 0x0 0x20000>;
1660
-		reg-io-width = <4>;
1661
-		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1662
-		interrupt-names = "hdmi", "hdmi_wakeup";
1663
-		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1664
-		clock-names = "iahb", "isfr", "cec";
1665
-		pinctrl-names = "default";
1666
-		pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
1667
-		resets = <&cru SRST_HDMI>;
1668
-		reset-names = "hdmi";
1669
-		power-domains = <&power RK3368_PD_VIO>;
1670
-		rockchip,grf = <&grf>;
1671
-		status = "disabled";
1672
-
1673
-		ports {
1674
-			port {
1675
-				hdmi_in_vop: endpoint {
1676
-					remote-endpoint = <&vop_out_hdmi>;
1677
-				};
1678
-			};
1679
-		};
1680
-	};
1681
-
1682
-	mpp_srv: mpp-srv {
1683
-		compatible = "rockchip,mpp-service";
1684
-		rockchip,taskqueue-count = <1>;
1685
-		rockchip,resetgroup-count = <1>;
1686
-		rockchip,grf = <&grf>;
1687
-		rockchip,grf-offset = <0x0418>;
1688
-		rockchip,grf-values = <0x10001000>, <0x10000000>, <0x10000000>;
1689
-		rockchip,grf-names = "grf_rkvdec", "grf_vdpu1", "grf_vepu1";
1690
-		status = "disabled";
1691
-	};
1692
-
1693
-	hevc: hevc_service@ff9a0000 {
1694
-		compatible = "rockchip,hevc-decoder-rk3368";
1695
-		reg = <0x0 0xff9a0000 0x0 0x400>;
1696
-		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1697
-		interrupt-names = "irq_dec";
1698
-		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1699
-			<&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1700
-		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1701
-				"clk_cabac";
1702
-		rockchip,normal-rates = <300000000>, <0>, <200000000>,
1703
-				<200000000>;
1704
-		rockchip,advanced-rates = <500000000>, <0>, <400000000>,
1705
-				<400000000>;
1706
-		resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1707
-			<&cru SRST_VIDEO>;
1708
-		reset-names = "shared_video_a", "shared_video_h", "video_core";
1709
-		iommus = <&hevc_mmu>;
1710
-		rockchip,srv = <&mpp_srv>;
1711
-		rockchip,taskqueue-node = <0>;
1712
-		rockchip,resetgroup-node = <0>;
1713
-		power-domains = <&power RK3368_PD_VIDEO>;
1714
-		status = "disabled";
1715
-	};
1716
-
1717
-	vepu: vepu@ff9a0000 {
1718
-		compatible = "rockchip,vpu-encoder-v1";
1719
-		reg = <0x0 0xff9a0000 0x0 0x400>;
1720
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1721
-		interrupt-names = "irq_enc";
1722
-		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1723
-		clock-names = "aclk_vcodec", "hclk_vcodec";
1724
-		resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>;
1725
-		reset-names = "shared_video_a", "shared_video_h";
1726
-		iommus = <&vpu_mmu>;
1727
-		power-domains = <&power RK3368_PD_VIDEO>;
1728
-		rockchip,srv = <&mpp_srv>;
1729
-		rockchip,taskqueue-node = <0>;
1730
-		rockchip,resetgroup-node = <0>;
1731
-		status = "disabled";
1732
-	};
1733
-
1734
-	vdpu: vdpu@ff9a0400 {
1735
-		compatible = "rockchip,vpu-decoder-rk3368";
1736
-		reg = <0x0 0xff9a0400 0x0 0x400>;
1737
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1738
-		interrupt-names = "irq_dec";
1739
-		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1740
-		clock-names = "aclk_vcodec", "hclk_vcodec";
1741
-		rockchip,normal-rates = <300000000>, <0>;
1742
-		rockchip,advanced-rates = <600000000>, <0>;
1743
-		resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>;
1744
-		reset-names = "shared_video_a", "shared_video_h";
1745
-		iommus = <&vpu_mmu>;
1746
-		power-domains = <&power RK3368_PD_VIDEO>;
1747
-		rockchip,srv = <&mpp_srv>;
1748
-		rockchip,taskqueue-node = <0>;
1749
-		rockchip,resetgroup-node = <0>;
1750753 		status = "disabled";
1751754 	};
1752755 
....@@ -1758,7 +761,6 @@
1758761 		interrupt-names = "hevc_mmu";
1759762 		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1760763 		clock-names = "aclk", "iface";
1761
-		power-domains = <&power RK3368_PD_VIDEO>;
1762764 		#iommu-cells = <0>;
1763765 		status = "disabled";
1764766 	};
....@@ -1766,14 +768,29 @@
1766768 	vpu_mmu: iommu@ff9a0800 {
1767769 		compatible = "rockchip,iommu";
1768770 		reg = <0x0 0xff9a0800 0x0 0x100>;
1769
-		interrupts =  <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1770
-			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
771
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
772
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1771773 		interrupt-names = "vepu_mmu", "vdpu_mmu";
1772774 		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1773775 		clock-names = "aclk", "iface";
1774
-		power-domains = <&power RK3368_PD_VIDEO>;
1775776 		#iommu-cells = <0>;
1776777 		status = "disabled";
778
+	};
779
+
780
+	efuse256: efuse@ffb00000 {
781
+		compatible = "rockchip,rk3368-efuse";
782
+		reg = <0x0 0xffb00000 0x0 0x20>;
783
+		#address-cells = <1>;
784
+		#size-cells = <1>;
785
+		clocks = <&cru PCLK_EFUSE256>;
786
+		clock-names = "pclk_efuse";
787
+
788
+		cpu_leakage: cpu-leakage@17 {
789
+			reg = <0x17 0x1>;
790
+		};
791
+		temp_adjust: temp-adjust@1f {
792
+			reg = <0x1f 0x1>;
793
+		};
1777794 	};
1778795 
1779796 	gic: interrupt-controller@ffb71000 {
....@@ -1788,114 +805,6 @@
1788805 		      <0x0 0xffb76000 0x0 0x2000>;
1789806 		interrupts = <GIC_PPI 9
1790807 		      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1791
-	};
1792
-
1793
-	gpu: rogue-g6110@ffa30000 {
1794
-		compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1795
-		reg = <0x0 0xffa30000 0x0 0x10000>;
1796
-		clocks =
1797
-			<&cru SCLK_GPU_CORE>,
1798
-			<&cru ACLK_GPU_MEM>,
1799
-			<&cru ACLK_GPU_CFG>;
1800
-		clock-names =
1801
-			"sclk_gpu_core",
1802
-			"aclk_gpu_mem",
1803
-			"aclk_gpu_cfg";
1804
-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1805
-		interrupt-names = "rogue-g6110-irq";
1806
-		power-domains = <&power RK3368_PD_GPU_1>;
1807
-		operating-points-v2 = <&gpu_opp_table>;
1808
-		#cooling-cells = <2>; /* min followed by max */
1809
-		gpu_power_model: power_model {
1810
-			compatible = "arm,mali-simple-power-model";
1811
-			voltage = <900>;
1812
-			frequency = <500>;
1813
-			static-power = <300>;
1814
-			dynamic-power = <396>;
1815
-			ts = <32000 4700 (-80) 2>;
1816
-			thermal-zone = "gpu-thermal";
1817
-		};
1818
-	};
1819
-
1820
-	gpu_opp_table: gpu_opp_table {
1821
-		compatible = "operating-points-v2";
1822
-		opp-shared;
1823
-
1824
-		opp-200000000 {
1825
-			opp-hz = /bits/ 64 <200000000>;
1826
-			opp-microvolt = <1100000>;
1827
-		};
1828
-		opp-288000000 {
1829
-			opp-hz = /bits/ 64 <288000000>;
1830
-			opp-microvolt = <1100000>;
1831
-		};
1832
-		opp-400000000 {
1833
-			opp-hz = /bits/ 64 <400000000>;
1834
-			opp-microvolt = <1100000>;
1835
-		};
1836
-		opp-576000000 {
1837
-			opp-hz = /bits/ 64 <576000000>;
1838
-			opp-microvolt = <1200000>;
1839
-		};
1840
-	};
1841
-
1842
-	nocp_peri: nocp-peri@ffac1000 {
1843
-		compatible = "rockchip,rk3368-nocp";
1844
-		reg = <0x0 0xffac1000 0x0 0x400>;
1845
-	};
1846
-
1847
-	nocp_core: nocp-core@ffac1400 {
1848
-		compatible = "rockchip,rk3368-nocp";
1849
-		reg = <0x0 0xffac1400 0x0 0x400>;
1850
-	};
1851
-
1852
-	nocp_gpu: nocp-gpu@ffac1800 {
1853
-		compatible = "rockchip,rk3368-nocp";
1854
-		reg = <0x0 0xffac1800 0x0 0x400>;
1855
-	};
1856
-
1857
-	nocp_vpu: nocp-vpu@ffac2000 {
1858
-		compatible = "rockchip,rk3368-nocp";
1859
-		reg = <0x0 0xffac2000 0x0 0x400>;
1860
-	};
1861
-
1862
-	nocp_vop: nocp-vop@ffac2400 {
1863
-		compatible = "rockchip,rk3368-nocp";
1864
-		reg = <0x0 0xffac2400 0x0 0x400>;
1865
-	};
1866
-
1867
-	nocp_rga: nocp-rga@ffac2800 {
1868
-		compatible = "rockchip,rk3368-nocp";
1869
-		reg = <0x0 0xffac2800 0x0 0x400>;
1870
-	};
1871
-
1872
-	efuse: efuse@ffb00000 {
1873
-		compatible = "rockchip,rk3368-efuse";
1874
-		reg = <0x0 0xffb00000 0x0 0x20>;
1875
-		#address-cells = <1>;
1876
-		#size-cells = <1>;
1877
-		clocks = <&cru PCLK_EFUSE256>;
1878
-		clock-names = "pclk_efuse";
1879
-
1880
-		/* Data cells */
1881
-		cpu_leakage: cpu-leakage@17 {
1882
-			reg = <0x17 0x1>;
1883
-		};
1884
-		leakage_volt: leakage-volt@1a {
1885
-			reg = <0x1a 0x1>;
1886
-			bits = <7 1>;
1887
-		};
1888
-		leakage_temp: leakage-temp@1e {
1889
-			reg = <0x1e 0x1>;
1890
-			bits = <1 7>;
1891
-		};
1892
-		temp_adjust: temp-adjust@1f {
1893
-			reg = <0x1f 0x1>;
1894
-		};
1895
-	};
1896
-
1897
-	rockchip_system_monitor: rockchip-system-monitor {
1898
-		compatible = "rockchip,system-monitor";
1899808 	};
1900809 
1901810 	pinctrl: pinctrl {
....@@ -1975,12 +884,6 @@
1975884 			drive-strength = <12>;
1976885 		};
1977886 
1978
-		edp {
1979
-			edp_hpd: edp-hpd {
1980
-				rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1981
-			};
1982
-		};
1983
-
1984887 		emmc {
1985888 			emmc_clk: emmc-clk {
1986889 				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
....@@ -2050,17 +953,6 @@
2050953 			};
2051954 		};
2052955 
2053
-		hdmi {
2054
-			hdmi_cec: hdmi-cec {
2055
-				rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
2056
-			};
2057
-
2058
-			hdmi_i2c_xfer: hdmi-i2c-xfer {
2059
-				rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>,
2060
-						<3 RK_PD3 1 &pcfg_pull_none>;
2061
-			};
2062
-		};
2063
-
2064956 		i2c0 {
2065957 			i2c0_xfer: i2c0-xfer {
2066958 				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
....@@ -2112,11 +1004,8 @@
21121004 						<2 RK_PC0 1 &pcfg_pull_none>,
21131005 						<2 RK_PC1 1 &pcfg_pull_none>,
21141006 						<2 RK_PC2 1 &pcfg_pull_none>,
2115
-						<2 RK_PC3 1 &pcfg_pull_none>;
2116
-			};
2117
-
2118
-			i2s_8ch_mclk: i2s-8ch-mclk {
2119
-				rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1007
+						<2 RK_PC3 1 &pcfg_pull_none>,
1008
+						<2 RK_PC4 1 &pcfg_pull_none>;
21201009 			};
21211010 		};
21221011 
....@@ -2221,8 +1110,8 @@
22211110 		};
22221111 
22231112 		spdif {
2224
-			spdif_bus: spdif-bus {
2225
-				rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1113
+			spdif_tx: spdif-tx {
1114
+				rockchip,pins =	<2 RK_PC7 1 &pcfg_pull_none>;
22261115 			};
22271116 		};
22281117 
....@@ -2277,10 +1166,20 @@
22771166 			};
22781167 		};
22791168 
1169
+		tsadc {
1170
+			otp_pin: otp-pin {
1171
+				rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1172
+			};
1173
+
1174
+			otp_out: otp-out {
1175
+				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1176
+			};
1177
+		};
1178
+
22801179 		uart0 {
22811180 			uart0_xfer: uart0-xfer {
22821181 				rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
2283
-						<2 RK_PD1 1 &pcfg_pull_up>;
1182
+						<2 RK_PD1 1 &pcfg_pull_none>;
22841183 			};
22851184 
22861185 			uart0_cts: uart0-cts {
....@@ -2295,7 +1194,7 @@
22951194 		uart1 {
22961195 			uart1_xfer: uart1-xfer {
22971196 				rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
2298
-						<0 RK_PC5 3 &pcfg_pull_up>;
1197
+						<0 RK_PC5 3 &pcfg_pull_none>;
22991198 			};
23001199 
23011200 			uart1_cts: uart1-cts {
....@@ -2310,7 +1209,7 @@
23101209 		uart2 {
23111210 			uart2_xfer: uart2-xfer {
23121211 				rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
2313
-						<2 RK_PA5 2 &pcfg_pull_up>;
1212
+						<2 RK_PA5 2 &pcfg_pull_none>;
23141213 			};
23151214 			/* no rts / cts for uart2 */
23161215 		};
....@@ -2318,7 +1217,7 @@
23181217 		uart3 {
23191218 			uart3_xfer: uart3-xfer {
23201219 				rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
2321
-						<3 RK_PD6 2 &pcfg_pull_up>;
1220
+						<3 RK_PD6 3 &pcfg_pull_none>;
23221221 			};
23231222 
23241223 			uart3_cts: uart3-cts {
....@@ -2333,7 +1232,7 @@
23331232 		uart4 {
23341233 			uart4_xfer: uart4-xfer {
23351234 				rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
2336
-						<0 RK_PD2 3 &pcfg_pull_up>;
1235
+						<0 RK_PD2 3 &pcfg_pull_none>;
23371236 			};
23381237 
23391238 			uart4_cts: uart4-cts {
....@@ -2344,149 +1243,5 @@
23441243 				rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
23451244 			};
23461245 		};
2347
-
2348
-		isp {
2349
-			cif_clkout: cif-clkout {
2350
-				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
2351
-			};
2352
-
2353
-			isp_dvp_d2d9: isp-dvp-d2d9 {
2354
-				rockchip,pins =
2355
-						<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
2356
-						<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
2357
-						<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
2358
-						<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
2359
-						<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
2360
-						<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
2361
-						<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
2362
-						<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
2363
-						<1 RK_PB0 1 &pcfg_pull_none>,//cif_sync
2364
-						<1 RK_PB1 1 &pcfg_pull_none>,//cif_href
2365
-						<1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin
2366
-						<1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
2367
-			};
2368
-
2369
-			isp_dvp_d0d1: isp-dvp-d0d1 {
2370
-				rockchip,pins =
2371
-						<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
2372
-						<1 RK_PB5 1 &pcfg_pull_none>;//cif_data1
2373
-			};
2374
-
2375
-			isp_dvp_d10d11:isp_d10d11 {
2376
-				rockchip,pins =
2377
-						<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
2378
-						<1 RK_PB7 1 &pcfg_pull_none>;//cif_data11
2379
-			};
2380
-
2381
-			isp_dvp_d0d7: isp-dvp-d0d7 {
2382
-				rockchip,pins =
2383
-						<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
2384
-						<1 RK_PB5 1 &pcfg_pull_none>,//cif_data1
2385
-						<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
2386
-						<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
2387
-						<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
2388
-						<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
2389
-						<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
2390
-						<1 RK_PA5 1 &pcfg_pull_none>;//cif_data7
2391
-			};
2392
-
2393
-			isp_dvp_d4d11: isp-dvp-d4d11 {
2394
-				rockchip,pins =
2395
-						<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
2396
-						<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
2397
-						<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
2398
-						<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
2399
-						<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
2400
-						<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
2401
-						<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
2402
-						<1 RK_PC1 1 &pcfg_pull_none>;//cif_data11
2403
-			};
2404
-
2405
-			isp_shutter: isp-shutter {
2406
-				rockchip,pins =
2407
-						<3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN
2408
-						<3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG
2409
-			};
2410
-
2411
-			isp_flash_trigger: isp-flash-trigger {
2412
-				rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2413
-			};
2414
-
2415
-			isp_prelight: isp-prelight {
2416
-				rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2417
-			};
2418
-
2419
-			isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2420
-				rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2421
-			};
2422
-		};
2423
-
2424
-		lcdc {
2425
-			lcdc_rgb_pins: lcdc-rgb-pins {
2426
-				rockchip,pins =
2427
-					<0 RK_PB6 1 &pcfg_pull_none>,  /* LCDC_D10 */
2428
-					<0 RK_PB7 1 &pcfg_pull_none>,  /* LCDC_D11 */
2429
-					<0 RK_PC0 1 &pcfg_pull_none>,  /* LCDC_D12 */
2430
-					<0 RK_PC1 1 &pcfg_pull_none>,  /* LCDC_D13 */
2431
-					<0 RK_PC2 1 &pcfg_pull_none>,  /* LCDC_D14 */
2432
-					<0 RK_PC3 1 &pcfg_pull_none>,  /* LCDC_D15 */
2433
-					<0 RK_PC4 1 &pcfg_pull_none>,  /* LCDC_D16 */
2434
-					<0 RK_PC5 1 &pcfg_pull_none>,  /* LCDC_D17 */
2435
-					<0 RK_PC6 1 &pcfg_pull_none>,  /* LCDC_D18 */
2436
-					<0 RK_PC7 1 &pcfg_pull_none>,  /* LCDC_D19 */
2437
-					<0 RK_PD0 1 &pcfg_pull_none>,  /* LCDC_D20 */
2438
-					<0 RK_PD1 1 &pcfg_pull_none>,  /* LCDC_D21 */
2439
-					<0 RK_PD2 1 &pcfg_pull_none>,  /* LCDC_D22 */
2440
-					<0 RK_PD3 1 &pcfg_pull_none>,  /* LCDC_D23 */
2441
-					<0 RK_PD7 1 &pcfg_pull_none>,  /* DCLK */
2442
-					<0 RK_PD6 1 &pcfg_pull_none>,  /* DEN */
2443
-					<0 RK_PD4 1 &pcfg_pull_none>,  /* HSYNC */
2444
-					<0 RK_PD5 1 &pcfg_pull_none>;  /* VSYNC */
2445
-			};
2446
-
2447
-			lcdc_sleep_pins: lcdc-sleep-pins {
2448
-				rockchip,pins =
2449
-					<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D10 */
2450
-					<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D11 */
2451
-					<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D12 */
2452
-					<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D13 */
2453
-					<0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D14 */
2454
-					<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D15 */
2455
-					<0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D16 */
2456
-					<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D17 */
2457
-					<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D18 */
2458
-					<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D19 */
2459
-					<0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D20 */
2460
-					<0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D21 */
2461
-					<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D22 */
2462
-					<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D23 */
2463
-					<0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>,  /* DCLK */
2464
-					<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,  /* DEN */
2465
-					<0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>,  /* HSYNC */
2466
-					<0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;  /* VSYNC */
2467
-			};
2468
-		};
2469
-	};
2470
-
2471
-	rockchip_suspend: rockchip-suspend {
2472
-		compatible = "rockchip,pm-rk3368";
2473
-		status = "disabled";
2474
-		rockchip,sleep-debug-en = <0>;
2475
-		rockchip,sleep-mode-config = <
2476
-			(0
2477
-			| RKPM_SLP_ARMOFF
2478
-			| RKPM_SLP_PMU_PLLS_PWRDN
2479
-			| RKPM_SLP_PMU_PMUALIVE_32K
2480
-			| RKPM_SLP_SFT_PLLS_DEEP
2481
-			| RKPM_SLP_PMU_DIS_OSC
2482
-			| RKPM_SLP_SFT_PD_NBSCUS
2483
-			)
2484
-		>;
2485
-		rockchip,wakeup-config = <
2486
-			(0
2487
-			| RKPM_GPIO_WKUP_EN
2488
-			| RKPM_USB_WKUP_EN
2489
-			)
2490
-		>;
24911246 	};
24921247 };