change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/arm/mach-davinci/dm644x.c
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@@ -14,6 +14,8 @@
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 #include <linux/clkdev.h>
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 #include <linux/dmaengine.h>
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 #include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/irqchip/irq-davinci-aintc.h>
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 #include <linux/platform_data/edma.h>
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 #include <linux/platform_data/gpio-davinci.h>
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 #include <linux/platform_device.h>
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@@ -23,13 +25,14 @@
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 #include <mach/common.h>
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 #include <mach/cputype.h>
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-#include <mach/irqs.h>
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 #include <mach/mux.h>
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 #include <mach/serial.h>
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-#include <mach/time.h>
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+
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+#include <clocksource/timer-davinci.h>
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 #include "asp.h"
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 #include "davinci.h"
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+#include "irqs.h"
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 #include "mux.h"
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 /*
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@@ -59,8 +62,8 @@
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 		.flags	= IORESOURCE_MEM,
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 	},
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 	{
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-		.start = IRQ_EMACINT,
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-		.end   = IRQ_EMACINT,
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+		.start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
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+		.end   = DAVINCI_INTC_IRQ(IRQ_EMACINT),
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 		.flags = IORESOURCE_IRQ,
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 	},
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 };
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@@ -260,12 +263,12 @@
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 	},
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 	{
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 		.name	= "edma3_ccint",
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-		.start	= IRQ_CCINT0,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_CCINT0),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 	{
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 		.name	= "edma3_ccerrint",
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-		.start	= IRQ_CCERRINT,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_CCERRINT),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 	/* not using TC*_ERR */
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@@ -330,13 +333,13 @@
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 static struct resource dm644x_vpfe_resources[] = {
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 	{
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-		.start          = IRQ_VDINT0,
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-		.end            = IRQ_VDINT0,
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+		.start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
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+		.end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
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 		.flags          = IORESOURCE_IRQ,
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 	},
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 	{
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-		.start          = IRQ_VDINT1,
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-		.end            = IRQ_VDINT1,
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+		.start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
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+		.end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
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 		.flags          = IORESOURCE_IRQ,
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 	},
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 };
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@@ -442,8 +445,8 @@
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 static struct resource dm644x_v4l2_disp_resources[] = {
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 	{
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-		.start	= IRQ_VENCINT,
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-		.end	= IRQ_VENCINT,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_VENCINT),
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+		.end	= DAVINCI_INTC_IRQ(IRQ_VENCINT),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 };
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@@ -491,33 +494,35 @@
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 		.flags	= IORESOURCE_MEM,
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 	},
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 	{	/* interrupt */
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-		.start	= IRQ_GPIOBNK0,
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-		.end	= IRQ_GPIOBNK0,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
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+		.end	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 	{
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-		.start	= IRQ_GPIOBNK1,
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-		.end	= IRQ_GPIOBNK1,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
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+		.end	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 	{
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-		.start	= IRQ_GPIOBNK2,
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-		.end	= IRQ_GPIOBNK2,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
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+		.end	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 	{
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-		.start	= IRQ_GPIOBNK3,
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-		.end	= IRQ_GPIOBNK3,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
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+		.end	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 	{
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-		.start	= IRQ_GPIOBNK4,
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-		.end	= IRQ_GPIOBNK4,
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+		.start	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
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+		.end	= DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
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 		.flags	= IORESOURCE_IRQ,
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 	},
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 };
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 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
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+	.no_auto_base	= true,
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+	.base		= 0,
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 	.ngpio		= 71,
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 };
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@@ -557,21 +562,21 @@
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 };
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 /*
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- * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
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- * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
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- * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
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- * T1_TOP: Timer 1, top   :  <unused>
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+ * Bottom half of timer0 is used for clockevent, top half is used for
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+ * clocksource.
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  */
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-static struct davinci_timer_info dm644x_timer_info = {
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-	.timers		= davinci_timer_instance,
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-	.clockevent_id	= T0_BOT,
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-	.clocksource_id	= T0_TOP,
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+static const struct davinci_timer_cfg dm644x_timer_cfg = {
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+	.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
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+	.irq = {
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+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
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+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
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+	},
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 };
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 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
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 	{
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 		.mapbase	= DAVINCI_UART0_BASE,
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-		.irq		= IRQ_UARTINT0,
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+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT0),
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 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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 				  UPF_IOREMAP,
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 		.iotype		= UPIO_MEM,
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@@ -584,7 +589,7 @@
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 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
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 	{
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 		.mapbase	= DAVINCI_UART1_BASE,
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-		.irq		= IRQ_UARTINT1,
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+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT1),
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 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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 				  UPF_IOREMAP,
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 		.iotype		= UPIO_MEM,
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@@ -597,7 +602,7 @@
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 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
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 	{
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 		.mapbase	= DAVINCI_UART2_BASE,
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-		.irq		= IRQ_UARTINT2,
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+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT2),
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 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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 				  UPF_IOREMAP,
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 		.iotype		= UPIO_MEM,
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@@ -643,11 +648,6 @@
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 	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
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 	.pinmux_pins		= dm644x_pins,
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 	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),
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-	.intc_base		= DAVINCI_ARM_INTC_BASE,
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-	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
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-	.intc_irq_prios 	= dm644x_default_priorities,
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-	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
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-	.timer_info		= &dm644x_timer_info,
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 	.emac_pdata		= &dm644x_emac_pdata,
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 	.sram_dma		= 0x00008000,
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 	.sram_len		= SZ_16K,
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@@ -669,6 +669,7 @@
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 {
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 	void __iomem *pll1, *psc;
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 	struct clk *clk;
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+	int rv;
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 	clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
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@@ -679,8 +680,13 @@
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 	dm644x_psc_init(NULL, psc);
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 	clk = clk_get(NULL, "timer0");
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+	if (WARN_ON(IS_ERR(clk))) {
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+		pr_err("Unable to get the timer clock\n");
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+		return;
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+	}
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-	davinci_timer_init(clk);
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+	rv = davinci_timer_register(clk, &dm644x_timer_cfg);
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+	WARN(rv, "Unable to register the timer: %d\n", rv);
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 }
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 static struct resource dm644x_pll2_resources[] = {
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@@ -727,6 +733,21 @@
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 	return 0;
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 }
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+static const struct davinci_aintc_config dm644x_aintc_config = {
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+	.reg = {
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+		.start		= DAVINCI_ARM_INTC_BASE,
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+		.end		= DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
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+		.flags		= IORESOURCE_MEM,
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+	},
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+	.num_irqs		= 64,
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+	.prios			= dm644x_default_priorities,
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+};
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+
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+void __init dm644x_init_irq(void)
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+{
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+	davinci_aintc_init(&dm644x_aintc_config);
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+}
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+
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 void __init dm644x_init_devices(void)
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 {
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 	struct platform_device *edma_pdev;