forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/arch/arm/mach-davinci/dm365.c
....@@ -19,6 +19,8 @@
1919 #include <linux/dma-mapping.h>
2020 #include <linux/dmaengine.h>
2121 #include <linux/init.h>
22
+#include <linux/io.h>
23
+#include <linux/irqchip/irq-davinci-aintc.h>
2224 #include <linux/platform_data/edma.h>
2325 #include <linux/platform_data/gpio-davinci.h>
2426 #include <linux/platform_data/keyscan-davinci.h>
....@@ -31,13 +33,14 @@
3133 
3234 #include <mach/common.h>
3335 #include <mach/cputype.h>
34
-#include <mach/irqs.h>
3536 #include <mach/mux.h>
3637 #include <mach/serial.h>
37
-#include <mach/time.h>
38
+
39
+#include <clocksource/timer-davinci.h>
3840 
3941 #include "asp.h"
4042 #include "davinci.h"
43
+#include "irqs.h"
4144 #include "mux.h"
4245 
4346 #define DM365_REF_FREQ		24000000	/* 24 MHz on the DM365 EVM */
....@@ -224,7 +227,7 @@
224227 		.flags = IORESOURCE_MEM,
225228 	},
226229 	{
227
-		.start = IRQ_DM365_SPIINT0_0,
230
+		.start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
228231 		.flags = IORESOURCE_IRQ,
229232 	},
230233 };
....@@ -266,48 +269,50 @@
266269 		.flags	= IORESOURCE_MEM,
267270 	},
268271 	{	/* interrupt */
269
-		.start	= IRQ_DM365_GPIO0,
270
-		.end	= IRQ_DM365_GPIO0,
272
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
273
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
271274 		.flags	= IORESOURCE_IRQ,
272275 	},
273276 	{
274
-		.start	= IRQ_DM365_GPIO1,
275
-		.end	= IRQ_DM365_GPIO1,
277
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
278
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
276279 		.flags	= IORESOURCE_IRQ,
277280 	},
278281 	{
279
-		.start	= IRQ_DM365_GPIO2,
280
-		.end	= IRQ_DM365_GPIO2,
282
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
283
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
281284 		.flags	= IORESOURCE_IRQ,
282285 	},
283286 	{
284
-		.start	= IRQ_DM365_GPIO3,
285
-		.end	= IRQ_DM365_GPIO3,
287
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
288
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
286289 		.flags	= IORESOURCE_IRQ,
287290 	},
288291 	{
289
-		.start	= IRQ_DM365_GPIO4,
290
-		.end	= IRQ_DM365_GPIO4,
292
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
293
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
291294 		.flags	= IORESOURCE_IRQ,
292295 	},
293296 	{
294
-		.start	= IRQ_DM365_GPIO5,
295
-		.end	= IRQ_DM365_GPIO5,
297
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
298
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
296299 		.flags	= IORESOURCE_IRQ,
297300 	},
298301 	{
299
-		.start	= IRQ_DM365_GPIO6,
300
-		.end	= IRQ_DM365_GPIO6,
302
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
303
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
301304 		.flags	= IORESOURCE_IRQ,
302305 	},
303306 	{
304
-		.start	= IRQ_DM365_GPIO7,
305
-		.end	= IRQ_DM365_GPIO7,
307
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
308
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
306309 		.flags	= IORESOURCE_IRQ,
307310 	},
308311 };
309312 
310313 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
314
+	.no_auto_base	= true,
315
+	.base		= 0,
311316 	.ngpio		= 104,
312317 	.gpio_unbanked	= 8,
313318 };
....@@ -334,23 +339,23 @@
334339 		.flags	= IORESOURCE_MEM,
335340 	},
336341 	{
337
-		.start	= IRQ_DM365_EMAC_RXTHRESH,
338
-		.end	= IRQ_DM365_EMAC_RXTHRESH,
342
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
343
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
339344 		.flags	= IORESOURCE_IRQ,
340345 	},
341346 	{
342
-		.start	= IRQ_DM365_EMAC_RXPULSE,
343
-		.end	= IRQ_DM365_EMAC_RXPULSE,
347
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
348
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
344349 		.flags	= IORESOURCE_IRQ,
345350 	},
346351 	{
347
-		.start	= IRQ_DM365_EMAC_TXPULSE,
348
-		.end	= IRQ_DM365_EMAC_TXPULSE,
352
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
353
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
349354 		.flags	= IORESOURCE_IRQ,
350355 	},
351356 	{
352
-		.start	= IRQ_DM365_EMAC_MISCPULSE,
353
-		.end	= IRQ_DM365_EMAC_MISCPULSE,
357
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
358
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
354359 		.flags	= IORESOURCE_IRQ,
355360 	},
356361 };
....@@ -516,12 +521,12 @@
516521 	},
517522 	{
518523 		.name	= "edma3_ccint",
519
-		.start	= IRQ_CCINT0,
524
+		.start	= DAVINCI_INTC_IRQ(IRQ_CCINT0),
520525 		.flags	= IORESOURCE_IRQ,
521526 	},
522527 	{
523528 		.name	= "edma3_ccerrint",
524
-		.start	= IRQ_CCERRINT,
529
+		.start	= DAVINCI_INTC_IRQ(IRQ_CCERRINT),
525530 		.flags	= IORESOURCE_IRQ,
526531 	},
527532 	/* not using TC*_ERR */
....@@ -595,7 +600,7 @@
595600 		.flags = IORESOURCE_MEM,
596601 	},
597602 	{
598
-		.start = IRQ_DM365_RTCINT,
603
+		.start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
599604 		.flags = IORESOURCE_IRQ,
600605 	},
601606 };
....@@ -625,8 +630,8 @@
625630 	},
626631 	{
627632 		/* interrupt */
628
-		.start = IRQ_DM365_KEYINT,
629
-		.end = IRQ_DM365_KEYINT,
633
+		.start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
634
+		.end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
630635 		.flags = IORESOURCE_IRQ,
631636 	},
632637 };
....@@ -656,10 +661,16 @@
656661 	},
657662 };
658663 
659
-static struct davinci_timer_info dm365_timer_info = {
660
-	.timers		= davinci_timer_instance,
661
-	.clockevent_id	= T0_BOT,
662
-	.clocksource_id	= T0_TOP,
664
+/*
665
+ * Bottom half of timer0 is used for clockevent, top half is used for
666
+ * clocksource.
667
+ */
668
+static const struct davinci_timer_cfg dm365_timer_cfg = {
669
+	.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
670
+	.irq = {
671
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
672
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
673
+	},
663674 };
664675 
665676 #define DM365_UART1_BASE	(IO_PHYS + 0x106000)
....@@ -667,7 +678,7 @@
667678 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
668679 	{
669680 		.mapbase	= DAVINCI_UART0_BASE,
670
-		.irq		= IRQ_UARTINT0,
681
+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT0),
671682 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
672683 				  UPF_IOREMAP,
673684 		.iotype		= UPIO_MEM,
....@@ -680,7 +691,7 @@
680691 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
681692 	{
682693 		.mapbase	= DM365_UART1_BASE,
683
-		.irq		= IRQ_UARTINT1,
694
+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT1),
684695 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
685696 				  UPF_IOREMAP,
686697 		.iotype		= UPIO_MEM,
....@@ -719,11 +730,6 @@
719730 	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
720731 	.pinmux_pins		= dm365_pins,
721732 	.pinmux_pins_num	= ARRAY_SIZE(dm365_pins),
722
-	.intc_base		= DAVINCI_ARM_INTC_BASE,
723
-	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
724
-	.intc_irq_prios		= dm365_default_priorities,
725
-	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
726
-	.timer_info		= &dm365_timer_info,
727733 	.emac_pdata		= &dm365_emac_pdata,
728734 	.sram_dma		= 0x00010000,
729735 	.sram_len		= SZ_32K,
....@@ -771,6 +777,7 @@
771777 {
772778 	void __iomem *pll1, *pll2, *psc;
773779 	struct clk *clk;
780
+	int rv;
774781 
775782 	clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
776783 
....@@ -784,8 +791,13 @@
784791 	dm365_psc_init(NULL, psc);
785792 
786793 	clk = clk_get(NULL, "timer0");
794
+	if (WARN_ON(IS_ERR(clk))) {
795
+		pr_err("Unable to get the timer clock\n");
796
+		return;
797
+	}
787798 
788
-	davinci_timer_init(clk);
799
+	rv = davinci_timer_register(clk, &dm365_timer_cfg);
800
+	WARN(rv, "Unable to register the timer: %d\n", rv);
789801 }
790802 
791803 void __init dm365_register_clocks(void)
....@@ -820,13 +832,13 @@
820832 
821833 static struct resource vpfe_resources[] = {
822834 	{
823
-		.start          = IRQ_VDINT0,
824
-		.end            = IRQ_VDINT0,
835
+		.start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
836
+		.end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
825837 		.flags          = IORESOURCE_IRQ,
826838 	},
827839 	{
828
-		.start          = IRQ_VDINT1,
829
-		.end            = IRQ_VDINT1,
840
+		.start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
841
+		.end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
830842 		.flags          = IORESOURCE_IRQ,
831843 	},
832844 };
....@@ -907,8 +919,8 @@
907919 
908920 static struct resource dm365_venc_resources[] = {
909921 	{
910
-		.start = IRQ_VENCINT,
911
-		.end   = IRQ_VENCINT,
922
+		.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
923
+		.end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
912924 		.flags = IORESOURCE_IRQ,
913925 	},
914926 	/* venc registers io space */
....@@ -927,8 +939,8 @@
927939 
928940 static struct resource dm365_v4l2_disp_resources[] = {
929941 	{
930
-		.start = IRQ_VENCINT,
931
-		.end   = IRQ_VENCINT,
942
+		.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
943
+		.end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
932944 		.flags = IORESOURCE_IRQ,
933945 	},
934946 	/* venc registers io space */
....@@ -1050,6 +1062,21 @@
10501062 	return 0;
10511063 }
10521064 
1065
+static const struct davinci_aintc_config dm365_aintc_config = {
1066
+	.reg = {
1067
+		.start		= DAVINCI_ARM_INTC_BASE,
1068
+		.end		= DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1069
+		.flags		= IORESOURCE_MEM,
1070
+	},
1071
+	.num_irqs		= 64,
1072
+	.prios			= dm365_default_priorities,
1073
+};
1074
+
1075
+void __init dm365_init_irq(void)
1076
+{
1077
+	davinci_aintc_init(&dm365_aintc_config);
1078
+}
1079
+
10531080 static int __init dm365_init_devices(void)
10541081 {
10551082 	struct platform_device *edma_pdev;