change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/arch/arm/kernel/entry-common.S
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@@ -1,11 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  *  linux/arch/arm/kernel/entry-common.S
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  *
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  *  Copyright (C) 2000 Russell King
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <asm/assembler.h>
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@@ -56,7 +53,7 @@
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 	cmp	r2, #TASK_SIZE
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 	blne	addr_limit_check_failed
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 	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
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-	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
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+	movs	r1, r1, lsl #16
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 	bne	fast_work_pending
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..
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@@ -93,7 +90,7 @@
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 	cmp	r2, #TASK_SIZE
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 	blne	addr_limit_check_failed
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 	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
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-	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
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+	movs	r1, r1, lsl #16
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 	beq	no_work_pending
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  UNWIND(.fnend		)
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 ENDPROC(ret_fast_syscall)
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@@ -134,7 +131,7 @@
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 	cmp	r2, #TASK_SIZE
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 	blne	addr_limit_check_failed
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 	ldr	r1, [tsk, #TI_FLAGS]
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-	tst	r1, #_TIF_WORK_MASK
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+	movs	r1, r1, lsl #16
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 	bne	slow_work_pending
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 no_work_pending:
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 	asm_trace_hardirqs_on save = 0
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@@ -166,12 +163,36 @@
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  */
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 	.align	5
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+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
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+ENTRY(vector_bhb_loop8_swi)
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+	sub	sp, sp, #PT_REGS_SIZE
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+	stmia	sp, {r0 - r12}
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+	mov	r8, #8
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+1:	b	2f
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+2:	subs	r8, r8, #1
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+	bne	1b
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+	dsb
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+	isb
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+	b	3f
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+ENDPROC(vector_bhb_loop8_swi)
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+
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+	.align	5
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+ENTRY(vector_bhb_bpiall_swi)
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+	sub	sp, sp, #PT_REGS_SIZE
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+	stmia	sp, {r0 - r12}
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+	mcr	p15, 0, r8, c7, c5, 6	@ BPIALL
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+	isb
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+	b	3f
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+ENDPROC(vector_bhb_bpiall_swi)
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+#endif
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+	.align	5
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 ENTRY(vector_swi)
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 #ifdef CONFIG_CPU_V7M
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 	v7m_exception_entry
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 #else
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 	sub	sp, sp, #PT_REGS_SIZE
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 	stmia	sp, {r0 - r12}			@ Calling r0 - r12
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+3:
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  ARM(	add	r8, sp, #S_PC		)
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  ARM(	stmdb	r8, {sp, lr}^		)	@ Calling sp, lr
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  THUMB(	mov	r8, sp			)
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@@ -373,7 +394,7 @@
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 		movhs	scno, #0
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 		csdb
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 #endif
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-		stmloia	sp, {r5, r6}		@ shuffle args
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+		stmialo	sp, {r5, r6}		@ shuffle args
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 		movlo	r0, r1
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 		movlo	r1, r2
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 		movlo	r2, r3