forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777 
 kernel/arch/arc/kernel/setup.c
....@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
74  */
85 
96 #include <linux/seq_file.h>
....@@ -11,17 +8,19 @@
118 #include <linux/delay.h>
129 #include <linux/root_dev.h>
1310 #include <linux/clk.h>
14
-#include <linux/clk-provider.h>
1511 #include <linux/clocksource.h>
1612 #include <linux/console.h>
1713 #include <linux/module.h>
1814 #include <linux/sizes.h>
1915 #include <linux/cpu.h>
16
+#include <linux/of_clk.h>
2017 #include <linux/of_fdt.h>
2118 #include <linux/of.h>
2219 #include <linux/cache.h>
20
+#include <uapi/linux/mount.h>
2321 #include <asm/sections.h>
2422 #include <asm/arcregs.h>
23
+#include <asm/asserts.h>
2524 #include <asm/tlb.h>
2625 #include <asm/setup.h>
2726 #include <asm/page.h>
....@@ -29,6 +28,7 @@
2928 #include <asm/unwind.h>
3029 #include <asm/mach_desc.h>
3130 #include <asm/smp.h>
31
+#include <asm/dsp-impl.h>
3232 
3333 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
3434 
....@@ -45,29 +45,26 @@
4545 
4646 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
4747 
48
-static const struct id_to_str arc_cpu_rel[] = {
48
+static const struct id_to_str arc_legacy_rel[] = {
49
+	/* ID.ARCVER,	Release */
4950 #ifdef CONFIG_ISA_ARCOMPACT
50
-	{ 0x34, "R4.10"},
51
-	{ 0x35, "R4.11"},
51
+	{ 0x34, 	"R4.10"},
52
+	{ 0x35, 	"R4.11"},
5253 #else
53
-	{ 0x51, "R2.0" },
54
-	{ 0x52, "R2.1" },
55
-	{ 0x53, "R3.0" },
56
-	{ 0x54, "R3.10a" },
54
+	{ 0x51, 	"R2.0" },
55
+	{ 0x52, 	"R2.1" },
56
+	{ 0x53,		"R3.0" },
5757 #endif
58
-	{ 0x00, NULL   }
58
+	{ 0x00,		NULL   }
5959 };
6060 
61
-static const struct id_to_str arc_cpu_nm[] = {
62
-#ifdef CONFIG_ISA_ARCOMPACT
63
-	{ 0x20, "ARC 600"   },
64
-	{ 0x30, "ARC 770"   },  /* 750 identified seperately */
65
-#else
66
-	{ 0x40, "ARC EM"  },
67
-	{ 0x50, "ARC HS38"  },
68
-	{ 0x54, "ARC HS48"  },
69
-#endif
70
-	{ 0x00, "Unknown"   }
61
+static const struct id_to_str arc_hs_ver54_rel[] = {
62
+	/* UARCH.MAJOR,	Release */
63
+	{  0,		"R3.10a"},
64
+	{  1,		"R3.50a"},
65
+	{  2,		"R3.60a"},
66
+	{  3,		"R4.00a"},
67
+	{  0xFF,	NULL   }
7168 };
7269 
7370 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
....@@ -117,30 +114,65 @@
117114 	}
118115 }
119116 
117
+static void decode_arc_core(struct cpuinfo_arc *cpu)
118
+{
119
+	struct bcr_uarch_build_arcv2 uarch;
120
+	const struct id_to_str *tbl;
121
+
122
+	if (cpu->core.family < 0x54) { /* includes arc700 */
123
+
124
+		for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
125
+			if (cpu->core.family == tbl->id) {
126
+				cpu->release = tbl->str;
127
+				break;
128
+			}
129
+		}
130
+
131
+		if (is_isa_arcompact())
132
+			cpu->name = "ARC700";
133
+		else if (tbl->str)
134
+			cpu->name = "HS38";
135
+		else
136
+			cpu->name = cpu->release = "Unknown";
137
+
138
+		return;
139
+	}
140
+
141
+	/*
142
+	 * Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
143
+	 * ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
144
+	 * releases only update it.
145
+	 */
146
+	READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
147
+
148
+	if (uarch.prod == 4) {
149
+		cpu->name = "HS48";
150
+		cpu->extn.dual = 1;
151
+
152
+	} else {
153
+		cpu->name = "HS38";
154
+	}
155
+
156
+	for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
157
+		if (uarch.maj == tbl->id) {
158
+			cpu->release = tbl->str;
159
+			break;
160
+		}
161
+	}
162
+}
163
+
120164 static void read_arc_build_cfg_regs(void)
121165 {
122166 	struct bcr_timer timer;
123167 	struct bcr_generic bcr;
124168 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
125
-	const struct id_to_str *tbl;
126169 	struct bcr_isa_arcv2 isa;
170
+	struct bcr_actionpoint ap;
127171 
128172 	FIX_PTR(cpu);
129173 
130174 	READ_BCR(AUX_IDENTITY, cpu->core);
131
-
132
-	for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
133
-		if (cpu->core.family == tbl->id) {
134
-			cpu->details = tbl->str;
135
-			break;
136
-		}
137
-	}
138
-
139
-	for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
140
-		if ((cpu->core.family & 0xF4) == tbl->id)
141
-			break;
142
-	}
143
-	cpu->name = tbl->str;
175
+	decode_arc_core(cpu);
144176 
145177 	READ_BCR(ARC_REG_TIMERS_BCR, timer);
146178 	cpu->extn.timer0 = timer.t0;
....@@ -150,16 +182,6 @@
150182 	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
151183 
152184 	READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
153
-
154
-	cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
155
-	cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
156
-	cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0;        /* 1,3 */
157
-	cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
158
-	cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
159
-	cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 :
160
-				IS_ENABLED(CONFIG_ARC_HAS_SWAPE);
161
-
162
-	READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
163185 
164186 	/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
165187 	read_decode_ccm_bcr(cpu);
....@@ -196,44 +218,28 @@
196218 		cpu->bpu.full = bpu.ft;
197219 		cpu->bpu.num_cache = 256 << bpu.bce;
198220 		cpu->bpu.num_pred = 2048 << bpu.pte;
221
+		cpu->bpu.ret_stk = 4 << bpu.rse;
199222 
200
-		if (cpu->core.family >= 0x54) {
223
+		/* if dual issue hardware, is it enabled ? */
224
+		if (cpu->extn.dual) {
225
+			unsigned int exec_ctrl;
201226 
202
-			struct bcr_uarch_build_arcv2 uarch;
203
-
204
-			/*
205
-			 * The first 0x54 core (uarch maj:min 0:1 or 0:2) was
206
-			 * dual issue only (HS4x). But next uarch rev (1:0)
207
-			 * allows it be configured for single issue (HS3x)
208
-			 * Ensure we fiddle with dual issue only on HS4x
209
-			 */
210
-			READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
211
-
212
-			if (uarch.prod == 4) {
213
-				unsigned int exec_ctrl;
214
-
215
-				/* dual issue hardware always present */
216
-				cpu->extn.dual = 1;
217
-
218
-				READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
219
-
220
-				/* dual issue hardware enabled ? */
221
-				cpu->extn.dual_enb = !(exec_ctrl & 1);
222
-
223
-			}
227
+			READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
228
+			cpu->extn.dual_enb = !(exec_ctrl & 1);
224229 		}
225230 	}
226231 
227
-	READ_BCR(ARC_REG_AP_BCR, bcr);
228
-	cpu->extn.ap = bcr.ver ? 1 : 0;
232
+	READ_BCR(ARC_REG_AP_BCR, ap);
233
+	if (ap.ver) {
234
+		cpu->extn.ap_num = 2 << ap.num;
235
+		cpu->extn.ap_full = !ap.min;
236
+	}
229237 
230238 	READ_BCR(ARC_REG_SMART_BCR, bcr);
231239 	cpu->extn.smart = bcr.ver ? 1 : 0;
232240 
233241 	READ_BCR(ARC_REG_RTT_BCR, bcr);
234242 	cpu->extn.rtt = bcr.ver ? 1 : 0;
235
-
236
-	cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
237243 
238244 	READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
239245 
....@@ -261,7 +267,8 @@
261267 {
262268 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
263269 	struct bcr_identity *core = &cpu->core;
264
-	int i, n = 0;
270
+	char mpy_opt[16];
271
+	int n = 0;
265272 
266273 	FIX_PTR(cpu);
267274 
....@@ -270,7 +277,7 @@
270277 		       core->family, core->cpu_id, core->chip_id);
271278 
272279 	n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
273
-		       cpu_id, cpu->name, cpu->details,
280
+		       cpu_id, cpu->name, cpu->release,
274281 		       is_isa_arcompact() ? "ARCompact" : "ARCv2",
275282 		       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
276283 		       IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
....@@ -281,58 +288,50 @@
281288 		       IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
282289 		       IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
283290 
284
-	n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
285
-			   IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
286
-			   IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
287
-			   IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));
288
-
289
-	if (i)
290
-		n += scnprintf(buf + n, len - n, "\n\t\t: ");
291
-
292291 	if (cpu->extn_mpy.ver) {
293
-		if (cpu->extn_mpy.ver <= 0x2) {	/* ARCompact */
294
-			n += scnprintf(buf + n, len - n, "mpy ");
292
+		if (is_isa_arcompact()) {
293
+			scnprintf(mpy_opt, 16, "mpy");
295294 		} else {
295
+
296296 			int opt = 2;	/* stock MPY/MPYH */
297297 
298298 			if (cpu->extn_mpy.dsp)	/* OPT 7-9 */
299299 				opt = cpu->extn_mpy.dsp + 6;
300300 
301
-			n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
301
+			scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
302302 		}
303303 	}
304304 
305305 	n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
306
-		       IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
307
-		       IS_AVAIL1(cpu->extn.norm, "norm "),
308
-		       IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
309
-		       IS_AVAIL1(cpu->extn.swap, "swap "),
310
-		       IS_AVAIL1(cpu->extn.minmax, "minmax "),
311
-		       IS_AVAIL1(cpu->extn.crc, "crc "),
312
-		       IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE));
306
+		       IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
307
+		       IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
308
+		       IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
309
+		       IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
310
+		       IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
313311 
314
-	if (cpu->bpu.ver)
312
+	if (cpu->bpu.ver) {
315313 		n += scnprintf(buf + n, len - n,
316
-			      "BPU\t\t: %s%s match, cache:%d, Predict Table:%d",
314
+			      "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
317315 			      IS_AVAIL1(cpu->bpu.full, "full"),
318316 			      IS_AVAIL1(!cpu->bpu.full, "partial"),
319
-			      cpu->bpu.num_cache, cpu->bpu.num_pred);
317
+			      cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
320318 
321
-	if (is_isa_arcv2()) {
322
-		struct bcr_lpb lpb;
319
+		if (is_isa_arcv2()) {
320
+			struct bcr_lpb lpb;
323321 
324
-		READ_BCR(ARC_REG_LPB_BUILD, lpb);
325
-		if (lpb.ver) {
326
-			unsigned int ctl;
327
-			ctl = read_aux_reg(ARC_REG_LPB_CTRL);
322
+			READ_BCR(ARC_REG_LPB_BUILD, lpb);
323
+			if (lpb.ver) {
324
+				unsigned int ctl;
325
+				ctl = read_aux_reg(ARC_REG_LPB_CTRL);
328326 
329
-			n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
330
-				lpb.entries,
331
-				IS_DISABLED_RUN(!ctl));
327
+				n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
328
+					       lpb.entries,
329
+					       IS_DISABLED_RUN(!ctl));
330
+			}
332331 		}
332
+		n += scnprintf(buf + n, len - n, "\n");
333333 	}
334334 
335
-	n += scnprintf(buf + n, len - n, "\n");
336335 	return buf;
337336 }
338337 
....@@ -350,11 +349,17 @@
350349 			       IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
351350 			       IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
352351 
353
-	if (cpu->extn.debug)
354
-		n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
355
-			       IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
352
+	if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
353
+		n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
356354 			       IS_AVAIL1(cpu->extn.smart, "smaRT "),
357355 			       IS_AVAIL1(cpu->extn.rtt, "RTT "));
356
+		if (cpu->extn.ap_num) {
357
+			n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
358
+				       cpu->extn.ap_num,
359
+				       cpu->extn.ap_full ? "full":"min");
360
+		}
361
+		n += scnprintf(buf + n, len - n, "\n");
362
+	}
358363 
359364 	if (cpu->dccm.sz || cpu->iccm.sz)
360365 		n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
....@@ -379,19 +384,27 @@
379384 		}
380385 	}
381386 
382
-	n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
383
-			EF_ARC_OSABI_CURRENT >> 8,
384
-			EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
385
-			"no-legacy-syscalls" : "64-bit data any register aligned");
386
-
387387 	return buf;
388
+}
389
+
390
+void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena)
391
+{
392
+	if (hw_exists && !opt_ena)
393
+		pr_warn(" ! Enable %s for working apps\n", opt_name);
394
+	else if (!hw_exists && opt_ena)
395
+		panic("Disable %s, hardware NOT present\n", opt_name);
396
+}
397
+
398
+void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena)
399
+{
400
+	if (!hw_exists && opt_ena)
401
+		panic("Disable %s, hardware NOT present\n", opt_name);
388402 }
389403 
390404 static void arc_chk_core_config(void)
391405 {
392406 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
393
-	int saved = 0, present = 0;
394
-	char *opt_nm = NULL;
407
+	int present = 0;
395408 
396409 	if (!cpu->extn.timer0)
397410 		panic("Timer0 is not present!\n");
....@@ -423,23 +436,16 @@
423436 	 */
424437 
425438 	if (is_isa_arcompact()) {
426
-		opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE";
427
-		saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
428
-
429439 		/* only DPDP checked since SP has no arch visible regs */
430440 		present = cpu->extn.fpu_dp;
441
+		CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present);
431442 	} else {
432
-		opt_nm = "CONFIG_ARC_HAS_ACCL_REGS";
433
-		saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS);
434
-
435443 		/* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
436444 		present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
437
-	}
445
+		CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present);
438446 
439
-	if (present && !saved)
440
-		pr_warn("Enable %s for working apps\n", opt_nm);
441
-	else if (!present && saved)
442
-		panic("Disable %s, hardware NOT present\n", opt_nm);
447
+		dsp_config_check();
448
+	}
443449 }
444450 
445451 /*
....@@ -569,10 +575,6 @@
569575 	 * But that is unlikely so keeping it as it is
570576 	 */
571577 	root_mountflags &= ~MS_RDONLY;
572
-
573
-#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
574
-	conswitchp = &dummy_con;
575
-#endif
576578 
577579 	arc_unwind_init();
578580 }