change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/Documentation/vm/mmu_notifier.rst
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@@ -89,7 +89,7 @@
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 So here because at time N+2 the clear page table entry was not pair with a
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 notification to invalidate the secondary TLB, the device see the new value for
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-addrB before seing the new value for addrA. This break total memory ordering
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+addrB before seeing the new value for addrA. This break total memory ordering
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 for the device.
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 When changing a pte to write protect or to point to a new write protected page