change otg to host mode

hc

2024-05-11 04dd17822334871b23ea2862f7798fb0e0007777

 kernel/Documentation/devicetree/bindings/pci/ti-pci.txt
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@@ -1,14 +1,21 @@
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 TI PCI Controllers
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 PCIe DesignWare Controller
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- - compatible: Should be "ti,dra7-pcie" for RC
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-	       Should be "ti,dra7-pcie-ep" for EP
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+ - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
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+	       Should be "ti,dra7-pcie-ep" for EP (deprecated)
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+	       Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
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+	       Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
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+	       Should be "ti,dra726-pcie-rc" for dra72x in RC mode
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+	       Should be "ti,dra726-pcie-ep" for dra72x in EP mode
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  - phys : list of PHY specifiers (used by generic PHY framework)
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  - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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 	       number of PHYs as specified in *phys* property.
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  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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 	       where <X> is the instance number of the pcie from the HW spec.
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  - num-lanes as specified in ../designware-pcie.txt
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+ - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
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+			module and the register offset to specify lane
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+			selection.
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 HOST MODE
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 =========
..
..
@@ -26,6 +33,11 @@
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    ranges,
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    interrupt-map-mask,
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    interrupt-map : as specified in ../designware-pcie.txt
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+ - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
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+			       should contain the register offset within syscon
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+			       and the 2nd argument should contain the bit field
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+			       for setting the bit to enable unaligned
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+			       access.
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 DEVICE MODE
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 ===========