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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c
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@@ -1,7 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  (C) 2010,2011       Thomas Renninger <trenn@suse.de>, Novell Inc.
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- *
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- *  Licensed under the terms of the GNU GPL License version 2.
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  */
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 #if defined(__i386__) || defined(__x86_64__)
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@@ -19,6 +18,10 @@
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 #define MSR_APERF	0xE8
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 #define MSR_MPERF	0xE7
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+
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+#define RDPRU ".byte 0x0f, 0x01, 0xfd"
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+#define RDPRU_ECX_MPERF	0
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+#define RDPRU_ECX_APERF	1
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 #define MSR_TSC	0x10
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@@ -87,15 +90,51 @@
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 	return ret;
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 }
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-static int mperf_init_stats(unsigned int cpu)
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+static int get_aperf_mperf(int cpu, unsigned long long *aval,
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+				    unsigned long long *mval)
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 {
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-	unsigned long long val;
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+	unsigned long low_a, high_a;
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+	unsigned long low_m, high_m;
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 	int ret;
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-	ret = read_msr(cpu, MSR_APERF, &val);
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-	aperf_previous_count[cpu] = val;
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-	ret |= read_msr(cpu, MSR_MPERF, &val);
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-	mperf_previous_count[cpu] = val;
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+	/*
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+	 * Running on the cpu from which we read the registers will
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+	 * prevent APERF/MPERF from going out of sync because of IPI
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+	 * latency introduced by read_msr()s.
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+	 */
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+	if (mperf_monitor.flags.per_cpu_schedule) {
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+		if (bind_cpu(cpu))
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+			return 1;
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+	}
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+
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+	if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_RDPRU) {
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+		asm volatile(RDPRU
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+			     : "=a" (low_a), "=d" (high_a)
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+			     : "c" (RDPRU_ECX_APERF));
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+		asm volatile(RDPRU
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+			     : "=a" (low_m), "=d" (high_m)
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+			     : "c" (RDPRU_ECX_MPERF));
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+
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+		*aval = ((low_a) | (high_a) << 32);
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+		*mval = ((low_m) | (high_m) << 32);
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+
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+		return 0;
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+	}
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+
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+	ret  = read_msr(cpu, MSR_APERF, aval);
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+	ret |= read_msr(cpu, MSR_MPERF, mval);
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+
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+	return ret;
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+}
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+
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+static int mperf_init_stats(unsigned int cpu)
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+{
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+	unsigned long long aval, mval;
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+	int ret;
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+
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+	ret = get_aperf_mperf(cpu, &aval, &mval);
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+	aperf_previous_count[cpu] = aval;
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+	mperf_previous_count[cpu] = mval;
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 	is_valid[cpu] = !ret;
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 	return 0;
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@@ -103,13 +142,12 @@
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142
 
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 static int mperf_measure_stats(unsigned int cpu)
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 {
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-	unsigned long long val;
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+	unsigned long long aval, mval;
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 	int ret;
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-	ret = read_msr(cpu, MSR_APERF, &val);
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-	aperf_current_count[cpu] = val;
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-	ret |= read_msr(cpu, MSR_MPERF, &val);
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-	mperf_current_count[cpu] = val;
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+	ret = get_aperf_mperf(cpu, &aval, &mval);
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+	aperf_current_count[cpu] = aval;
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+	mperf_current_count[cpu] = mval;
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 	is_valid[cpu] = !ret;
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 	return 0;
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@@ -241,7 +279,8 @@
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 	if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_INV_TSC))
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 		goto use_sysfs;
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-	if (cpupower_cpu_info.vendor == X86_VENDOR_AMD) {
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+	if (cpupower_cpu_info.vendor == X86_VENDOR_AMD ||
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+	    cpupower_cpu_info.vendor == X86_VENDOR_HYGON) {
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 		/* MSR_AMD_HWCR tells us whether TSC runs at P0/mperf
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 		 * freq.
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 		 * A test whether hwcr is accessable/available would be:
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@@ -305,6 +344,9 @@
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 	if (init_maxfreq_mode())
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 		return NULL;
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+	if (cpupower_cpu_info.vendor == X86_VENDOR_AMD)
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+		mperf_monitor.flags.per_cpu_schedule = 1;
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+
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 	/* Free this at program termination */
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 	is_valid = calloc(cpu_count, sizeof(int));
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 	mperf_previous_count = calloc(cpu_count, sizeof(unsigned long long));
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@@ -333,7 +375,7 @@
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 	.stop			= mperf_stop,
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 	.do_register		= mperf_register,
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 	.unregister		= mperf_unregister,
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-	.needs_root		= 1,
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+	.flags.needs_root	= 1,
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 	.overflow_s		= 922000000 /* 922337203 seconds TSC overflow
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 					       at 20GHz */
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 };