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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/sound/soc/codecs/wm8994.c
....@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * wm8994.c  --  WM8994 ALSA SoC Audio driver
34  *
45  * Copyright 2009-12 Wolfson Microelectronics plc
56  *
67  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7
- *
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as
11
- * published by the Free Software Foundation.
128  */
139 
1410 #include <linux/module.h>
....@@ -47,10 +43,12 @@
4743 #define WM8994_NUM_DRC 3
4844 #define WM8994_NUM_EQ  3
4945 
50
-static struct {
46
+struct wm8994_reg_mask {
5147 	unsigned int reg;
5248 	unsigned int mask;
53
-} wm8994_vu_bits[] = {
49
+};
50
+
51
+static struct wm8994_reg_mask wm8994_vu_bits[] = {
5452 	{ WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
5553 	{ WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
5654 	{ WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
....@@ -64,20 +62,24 @@
6462 
6563 	{ WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
6664 	{ WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67
-	{ WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68
-	{ WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
6965 	{ WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
7066 	{ WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
7167 	{ WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
7268 	{ WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73
-	{ WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74
-	{ WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
7569 	{ WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
7670 	{ WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
7771 	{ WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
7872 	{ WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
7973 	{ WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
8074 	{ WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
75
+};
76
+
77
+/* VU bitfields for ADC2, DAC2 not available on WM1811 */
78
+static struct wm8994_reg_mask wm8994_adc2_dac2_vu_bits[] = {
79
+	{ WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
80
+	{ WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
81
+	{ WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
82
+	{ WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
8183 };
8284 
8385 static int wm8994_drc_base[] = {
....@@ -117,7 +119,7 @@
117119 
118120 	idle = !wm8994->jack_mic;
119121 
120
-	sysclk = snd_soc_component_read32(component, WM8994_CLOCKING_1);
122
+	sysclk = snd_soc_component_read(component, WM8994_CLOCKING_1);
121123 	if (sysclk & WM8994_SYSCLK_SRC)
122124 		sysclk = wm8994->aifclk[1];
123125 	else
....@@ -171,12 +173,12 @@
171173 
172174 	switch (wm8994->sysclk[aif]) {
173175 	case WM8994_SYSCLK_MCLK1:
174
-		rate = wm8994->mclk[0];
176
+		rate = wm8994->mclk_rate[0];
175177 		break;
176178 
177179 	case WM8994_SYSCLK_MCLK2:
178180 		reg1 |= 0x8;
179
-		rate = wm8994->mclk[1];
181
+		rate = wm8994->mclk_rate[1];
180182 		break;
181183 
182184 	case WM8994_SYSCLK_FLL1:
....@@ -251,7 +253,7 @@
251253 			 struct snd_soc_dapm_widget *sink)
252254 {
253255 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
254
-	int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1);
256
+	int reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
255257 	const char *clk;
256258 
257259 	/* Check what we're currently using for CLK_SYS */
....@@ -289,7 +291,6 @@
289291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
290292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
291293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
292
-static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
293294 
294295 #define WM8994_DRC_SWITCH(xname, reg, shift) \
295296 	SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
....@@ -310,7 +311,7 @@
310311 	else
311312 		mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
312313 
313
-	ret = snd_soc_component_read32(component, mc->reg);
314
+	ret = snd_soc_component_read(component, mc->reg);
314315 	if (ret < 0)
315316 		return ret;
316317 	if (ret & mask)
....@@ -329,7 +330,7 @@
329330 	int save, i;
330331 
331332 	/* Save any enables; the configuration should clear them. */
332
-	save = snd_soc_component_read32(component, base);
333
+	save = snd_soc_component_read(component, base);
333334 	save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
334335 		WM8994_AIF1ADC1R_DRC_ENA;
335336 
....@@ -439,7 +440,7 @@
439440 	/* The EQ will be disabled while reconfiguring it, remember the
440441 	 * current configuration.
441442 	 */
442
-	save = snd_soc_component_read32(component, base);
443
+	save = snd_soc_component_read(component, base);
443444 	save &= WM8994_AIF1DAC1_EQ_ENA;
444445 
445446 	for (i = 0; i < WM8994_EQ_REGS; i++)
....@@ -737,13 +738,6 @@
737738 	       7, 1, ng_tlv),
738739 };
739740 
740
-static const struct snd_kcontrol_new wm1811_snd_controls[] = {
741
-SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
742
-	       mixin_boost_tlv),
743
-SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
744
-	       mixin_boost_tlv),
745
-};
746
-
747741 /* We run all mode setting through a function to enforce audio mode */
748742 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
749743 {
....@@ -865,7 +859,7 @@
865859 		switch (wm8994->vmid_mode) {
866860 		default:
867861 			WARN_ON(NULL == "Invalid VMID mode");
868
-			/* fall through */
862
+			fallthrough;
869863 		case WM8994_VMID_NORMAL:
870864 			/* Startup bias, VMID ramp & buffer */
871865 			snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
....@@ -1010,7 +1004,7 @@
10101004 	int reg, reg_r;
10111005 
10121006 	/* We also need the same AIF source for L/R and only one path */
1013
-	reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
1007
+	reg = snd_soc_component_read(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
10141008 	switch (reg) {
10151009 	case WM8994_AIF2DACL_TO_DAC1L:
10161010 		dev_vdbg(component->dev, "Class W source AIF2DAC\n");
....@@ -1029,7 +1023,7 @@
10291023 		return false;
10301024 	}
10311025 
1032
-	reg_r = snd_soc_component_read32(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1026
+	reg_r = snd_soc_component_read(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
10331027 	if (reg_r != reg) {
10341028 		dev_vdbg(component->dev, "Left and right DAC mixers different\n");
10351029 		return false;
....@@ -1042,6 +1036,65 @@
10421036 	return true;
10431037 }
10441038 
1039
+static void wm8994_update_vu_bits(struct snd_soc_component *component)
1040
+{
1041
+	struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1042
+	struct wm8994 *control = wm8994->wm8994;
1043
+	int i;
1044
+
1045
+	for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1046
+		snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1047
+					snd_soc_component_read(component,
1048
+						       wm8994_vu_bits[i].reg));
1049
+	if (control->type == WM1811)
1050
+		return;
1051
+
1052
+	for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++)
1053
+		snd_soc_component_write(component,
1054
+				wm8994_adc2_dac2_vu_bits[i].reg,
1055
+				snd_soc_component_read(component,
1056
+					wm8994_adc2_dac2_vu_bits[i].reg));
1057
+}
1058
+
1059
+static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable)
1060
+{
1061
+	struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1062
+	unsigned int offset, val, clk_idx;
1063
+	int ret;
1064
+
1065
+	if (aif)
1066
+		offset = 4;
1067
+	else
1068
+		offset = 0;
1069
+
1070
+	val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset);
1071
+	val &= WM8994_AIF1CLK_SRC_MASK;
1072
+
1073
+	switch (val) {
1074
+	case 0:
1075
+		clk_idx = WM8994_MCLK1;
1076
+		break;
1077
+	case 1:
1078
+		clk_idx = WM8994_MCLK2;
1079
+		break;
1080
+	default:
1081
+		return 0;
1082
+	}
1083
+
1084
+	if (enable) {
1085
+		ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
1086
+		if (ret < 0) {
1087
+			dev_err(component->dev,	"Failed to enable MCLK%d\n",
1088
+				clk_idx);
1089
+			return ret;
1090
+		}
1091
+	} else {
1092
+		clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
1093
+	}
1094
+
1095
+	return 0;
1096
+}
1097
+
10451098 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
10461099 		      struct snd_kcontrol *kcontrol, int event)
10471100 {
....@@ -1049,7 +1102,7 @@
10491102 	struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
10501103 	struct wm8994 *control = wm8994->wm8994;
10511104 	int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1052
-	int i;
1105
+	int ret;
10531106 	int dac;
10541107 	int adc;
10551108 	int val;
....@@ -1065,11 +1118,15 @@
10651118 
10661119 	switch (event) {
10671120 	case SND_SOC_DAPM_PRE_PMU:
1121
+		ret = aif_mclk_set(component, 0, true);
1122
+		if (ret < 0)
1123
+			return ret;
1124
+
10681125 		/* Don't enable timeslot 2 if not in use */
10691126 		if (wm8994->channels[0] <= 2)
10701127 			mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
10711128 
1072
-		val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_1);
1129
+		val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_1);
10731130 		if ((val & WM8994_AIF1ADCL_SRC) &&
10741131 		    (val & WM8994_AIF1ADCR_SRC))
10751132 			adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
....@@ -1080,7 +1137,7 @@
10801137 			adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
10811138 				WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
10821139 
1083
-		val = snd_soc_component_read32(component, WM8994_AIF1_CONTROL_2);
1140
+		val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_2);
10841141 		if ((val & WM8994_AIF1DACL_SRC) &&
10851142 		    (val & WM8994_AIF1DACR_SRC))
10861143 			dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
....@@ -1113,10 +1170,7 @@
11131170 		break;
11141171 
11151172 	case SND_SOC_DAPM_POST_PMU:
1116
-		for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1117
-			snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1118
-				      snd_soc_component_read32(component,
1119
-						   wm8994_vu_bits[i].reg));
1173
+		wm8994_update_vu_bits(component);
11201174 		break;
11211175 
11221176 	case SND_SOC_DAPM_PRE_PMD:
....@@ -1126,7 +1180,7 @@
11261180 		snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
11271181 				    mask, 0);
11281182 
1129
-		val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1183
+		val = snd_soc_component_read(component, WM8994_CLOCKING_1);
11301184 		if (val & WM8994_AIF2DSPCLK_ENA)
11311185 			val = WM8994_SYSDSPCLK_ENA;
11321186 		else
....@@ -1137,6 +1191,12 @@
11371191 		break;
11381192 	}
11391193 
1194
+	switch (event) {
1195
+	case SND_SOC_DAPM_POST_PMD:
1196
+		aif_mclk_set(component, 0, false);
1197
+		break;
1198
+	}
1199
+
11401200 	return 0;
11411201 }
11421202 
....@@ -1144,14 +1204,18 @@
11441204 		      struct snd_kcontrol *kcontrol, int event)
11451205 {
11461206 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1147
-	int i;
1207
+	int ret;
11481208 	int dac;
11491209 	int adc;
11501210 	int val;
11511211 
11521212 	switch (event) {
11531213 	case SND_SOC_DAPM_PRE_PMU:
1154
-		val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1);
1214
+		ret = aif_mclk_set(component, 1, true);
1215
+		if (ret < 0)
1216
+			return ret;
1217
+
1218
+		val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_1);
11551219 		if ((val & WM8994_AIF2ADCL_SRC) &&
11561220 		    (val & WM8994_AIF2ADCR_SRC))
11571221 			adc = WM8994_AIF2ADCR_ENA;
....@@ -1162,7 +1226,7 @@
11621226 			adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
11631227 
11641228 
1165
-		val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_2);
1229
+		val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_2);
11661230 		if ((val & WM8994_AIF2DACL_SRC) &&
11671231 		    (val & WM8994_AIF2DACR_SRC))
11681232 			dac = WM8994_AIF2DACR_ENA;
....@@ -1196,10 +1260,7 @@
11961260 		break;
11971261 
11981262 	case SND_SOC_DAPM_POST_PMU:
1199
-		for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1200
-			snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1201
-				      snd_soc_component_read32(component,
1202
-						   wm8994_vu_bits[i].reg));
1263
+		wm8994_update_vu_bits(component);
12031264 		break;
12041265 
12051266 	case SND_SOC_DAPM_PRE_PMD:
....@@ -1211,7 +1272,7 @@
12111272 				    WM8994_AIF2ADCL_ENA |
12121273 				    WM8994_AIF2ADCR_ENA, 0);
12131274 
1214
-		val = snd_soc_component_read32(component, WM8994_CLOCKING_1);
1275
+		val = snd_soc_component_read(component, WM8994_CLOCKING_1);
12151276 		if (val & WM8994_AIF1DSPCLK_ENA)
12161277 			val = WM8994_SYSDSPCLK_ENA;
12171278 		else
....@@ -1219,6 +1280,12 @@
12191280 		snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
12201281 				    WM8994_SYSDSPCLK_ENA |
12211282 				    WM8994_AIF2DSPCLK_ENA, val);
1283
+		break;
1284
+	}
1285
+
1286
+	switch (event) {
1287
+	case SND_SOC_DAPM_POST_PMD:
1288
+		aif_mclk_set(component, 1, false);
12221289 		break;
12231290 	}
12241291 
....@@ -1382,7 +1449,7 @@
13821449 {
13831450 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
13841451 	dev_dbg(component->dev, "SRC status: %x\n",
1385
-		snd_soc_component_read32(component,
1452
+		snd_soc_component_read(component,
13861453 			     WM8994_RATE_STATUS));
13871454 	return 0;
13881455 }
....@@ -1627,10 +1694,10 @@
16271694 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
16281695 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
16291696 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1630
-		    SND_SOC_DAPM_PRE_PMD),
1697
+		    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
16311698 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
16321699 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1633
-		    SND_SOC_DAPM_PRE_PMD),
1700
+		    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
16341701 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
16351702 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
16361703 		   left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
....@@ -2145,6 +2212,7 @@
21452212 	u16 reg, clk1, aif_reg, aif_src;
21462213 	unsigned long timeout;
21472214 	bool was_enabled;
2215
+	struct clk *mclk;
21482216 
21492217 	switch (id) {
21502218 	case WM8994_FLL1:
....@@ -2161,7 +2229,7 @@
21612229 		return -EINVAL;
21622230 	}
21632231 
2164
-	reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset);
2232
+	reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset);
21652233 	was_enabled = reg & WM8994_FLL1_ENA;
21662234 
21672235 	switch (src) {
....@@ -2202,12 +2270,12 @@
22022270 		return ret;
22032271 
22042272 	/* Make sure that we're not providing SYSCLK right now */
2205
-	clk1 = snd_soc_component_read32(component, WM8994_CLOCKING_1);
2273
+	clk1 = snd_soc_component_read(component, WM8994_CLOCKING_1);
22062274 	if (clk1 & WM8994_SYSCLK_SRC)
22072275 		aif_reg = WM8994_AIF2_CLOCKING_1;
22082276 	else
22092277 		aif_reg = WM8994_AIF1_CLOCKING_1;
2210
-	reg = snd_soc_component_read32(component, aif_reg);
2278
+	reg = snd_soc_component_read(component, aif_reg);
22112279 
22122280 	if ((reg & WM8994_AIF1CLK_ENA) &&
22132281 	    (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
....@@ -2219,6 +2287,27 @@
22192287 	/* We always need to disable the FLL while reconfiguring */
22202288 	snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
22212289 			    WM8994_FLL1_ENA, 0);
2290
+
2291
+	/* Disable MCLK if needed before we possibly change to new clock parent */
2292
+	if (was_enabled) {
2293
+		reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_5
2294
+							+ reg_offset);
2295
+		reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK)
2296
+			>> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1;
2297
+
2298
+		switch (reg) {
2299
+		case WM8994_FLL_SRC_MCLK1:
2300
+			mclk = wm8994->mclk[WM8994_MCLK1].clk;
2301
+			break;
2302
+		case WM8994_FLL_SRC_MCLK2:
2303
+			mclk = wm8994->mclk[WM8994_MCLK2].clk;
2304
+			break;
2305
+		default:
2306
+			mclk = NULL;
2307
+		}
2308
+
2309
+		clk_disable_unprepare(mclk);
2310
+	}
22222311 
22232312 	if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
22242313 	    freq_in == freq_out && freq_out) {
....@@ -2264,10 +2353,29 @@
22642353 	/* Clear any pending completion from a previous failure */
22652354 	try_wait_for_completion(&wm8994->fll_locked[id]);
22662355 
2356
+	switch (src) {
2357
+	case WM8994_FLL_SRC_MCLK1:
2358
+		mclk = wm8994->mclk[WM8994_MCLK1].clk;
2359
+		break;
2360
+	case WM8994_FLL_SRC_MCLK2:
2361
+		mclk = wm8994->mclk[WM8994_MCLK2].clk;
2362
+		break;
2363
+	default:
2364
+		mclk = NULL;
2365
+	}
2366
+
22672367 	/* Enable (with fractional mode if required) */
22682368 	if (freq_out) {
2369
+		ret = clk_prepare_enable(mclk);
2370
+		if (ret < 0) {
2371
+			dev_err(component->dev, "Failed to enable MCLK for FLL%d\n",
2372
+				id + 1);
2373
+			return ret;
2374
+		}
2375
+
22692376 		/* Enable VMID if we need it */
22702377 		if (!was_enabled) {
2378
+
22712379 			active_reference(component);
22722380 
22732381 			switch (control->type) {
....@@ -2335,9 +2443,9 @@
23352443 	if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
23362444 		dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
23372445 
2338
-		wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2446
+		wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
23392447 			& WM8994_AIF1CLK_RATE_MASK;
2340
-		wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2448
+		wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
23412449 			& WM8994_AIF1CLK_RATE_MASK;
23422450 
23432451 		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
....@@ -2376,12 +2484,29 @@
23762484 	return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
23772485 }
23782486 
2487
+static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id,
2488
+				unsigned int *freq)
2489
+{
2490
+	int ret;
2491
+
2492
+	if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id])
2493
+		return 0;
2494
+
2495
+	ret = clk_set_rate(wm8994->mclk[id].clk, *freq);
2496
+	if (ret < 0)
2497
+		return ret;
2498
+
2499
+	*freq = clk_get_rate(wm8994->mclk[id].clk);
2500
+
2501
+	return 0;
2502
+}
2503
+
23792504 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
23802505 		int clk_id, unsigned int freq, int dir)
23812506 {
23822507 	struct snd_soc_component *component = dai->component;
23832508 	struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2384
-	int i;
2509
+	int ret, i;
23852510 
23862511 	switch (dai->id) {
23872512 	case 1:
....@@ -2396,7 +2521,12 @@
23962521 	switch (clk_id) {
23972522 	case WM8994_SYSCLK_MCLK1:
23982523 		wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2399
-		wm8994->mclk[0] = freq;
2524
+
2525
+		ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
2526
+		if (ret < 0)
2527
+			return ret;
2528
+
2529
+		wm8994->mclk_rate[0] = freq;
24002530 		dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
24012531 			dai->id, freq);
24022532 		break;
....@@ -2404,7 +2534,12 @@
24042534 	case WM8994_SYSCLK_MCLK2:
24052535 		/* TODO: Set GPIO AF */
24062536 		wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2407
-		wm8994->mclk[1] = freq;
2537
+
2538
+		ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
2539
+		if (ret < 0)
2540
+			return ret;
2541
+
2542
+		wm8994->mclk_rate[1] = freq;
24082543 		dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
24092544 			dai->id, freq);
24102545 		break;
....@@ -2452,9 +2587,9 @@
24522587 	if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
24532588 		dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
24542589 
2455
-		wm8994->aifdiv[0] = snd_soc_component_read32(component, WM8994_AIF1_RATE)
2590
+		wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
24562591 			& WM8994_AIF1CLK_RATE_MASK;
2457
-		wm8994->aifdiv[1] = snd_soc_component_read32(component, WM8994_AIF2_RATE)
2592
+		wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
24582593 			& WM8994_AIF1CLK_RATE_MASK;
24592594 
24602595 		snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
....@@ -2661,7 +2796,7 @@
26612796 	case SND_SOC_DAIFMT_DSP_B:
26622797 		aif1 |= WM8994_AIF1_LRCLK_INV;
26632798 		lrclk |= WM8958_AIF1_LRCLK_INV;
2664
-		/* fall through */
2799
+		fallthrough;
26652800 	case SND_SOC_DAIFMT_DSP_A:
26662801 		aif1 |= 0x18;
26672802 		break;
....@@ -2876,7 +3011,7 @@
28763011 		dai->id, wm8994->aifclk[id], bclk_rate);
28773012 
28783013 	if (wm8994->channels[id] == 1 &&
2879
-	    (snd_soc_component_read32(component, aif1_reg) & 0x18) == 0x18)
3014
+	    (snd_soc_component_read(component, aif1_reg) & 0x18) == 0x18)
28803015 		aif2 |= WM8994_AIF1_MONO;
28813016 
28823017 	if (wm8994->aifclk[id] == 0) {
....@@ -2995,7 +3130,8 @@
29953130 	return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
29963131 }
29973132 
2998
-static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3133
+static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute,
3134
+			   int direction)
29993135 {
30003136 	struct snd_soc_component *component = codec_dai->component;
30013137 	int mute_reg;
....@@ -3072,18 +3208,20 @@
30723208 	.set_sysclk	= wm8994_set_dai_sysclk,
30733209 	.set_fmt	= wm8994_set_dai_fmt,
30743210 	.hw_params	= wm8994_hw_params,
3075
-	.digital_mute	= wm8994_aif_mute,
3211
+	.mute_stream	= wm8994_aif_mute,
30763212 	.set_pll	= wm8994_set_fll,
30773213 	.set_tristate	= wm8994_set_tristate,
3214
+	.no_capture_mute = 1,
30783215 };
30793216 
30803217 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
30813218 	.set_sysclk	= wm8994_set_dai_sysclk,
30823219 	.set_fmt	= wm8994_set_dai_fmt,
30833220 	.hw_params	= wm8994_hw_params,
3084
-	.digital_mute   = wm8994_aif_mute,
3221
+	.mute_stream	= wm8994_aif_mute,
30853222 	.set_pll	= wm8994_set_fll,
30863223 	.set_tristate	= wm8994_set_tristate,
3224
+	.no_capture_mute = 1,
30873225 };
30883226 
30893227 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
....@@ -3684,7 +3822,7 @@
36843822 
36853823 	mutex_lock(&wm8994->accdet_lock);
36863824 
3687
-	reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
3825
+	reg = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
36883826 	if (reg < 0) {
36893827 		dev_err(component->dev, "Failed to read jack status: %d\n", reg);
36903828 		mutex_unlock(&wm8994->accdet_lock);
....@@ -3766,6 +3904,10 @@
37663904  *
37673905  * @component:   WM8958 component
37683906  * @jack:    jack to report detection events on
3907
+ * @det_cb: detection callback
3908
+ * @det_cb_data: data for detection callback
3909
+ * @id_cb: mic id callback
3910
+ * @id_cb_data: data for mic id callback
37693911  *
37703912  * Enable microphone detection functionality for the WM8958.  By
37713913  * default simple detection which supports the detection of up to 6
....@@ -3899,7 +4041,7 @@
38994041 	 * with an update of the MICDET status; if so it will have
39004042 	 * stopped detection and we can ignore this interrupt.
39014043 	 */
3902
-	if (!(snd_soc_component_read32(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
4044
+	if (!(snd_soc_component_read(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
39034045 		return IRQ_HANDLED;
39044046 
39054047 	cancel_delayed_work_sync(&wm8994->mic_complete_work);
....@@ -3912,7 +4054,7 @@
39124054 	 */
39134055 	count = 10;
39144056 	do {
3915
-		reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3);
4057
+		reg = snd_soc_component_read(component, WM8958_MIC_DETECT_3);
39164058 		if (reg < 0) {
39174059 			dev_err(component->dev,
39184060 				"Failed to read mic detect status: %d\n",
....@@ -3941,7 +4083,7 @@
39414083 
39424084 	/* Avoid a transient report when the accessory is being removed */
39434085 	if (wm8994->jackdet) {
3944
-		ret = snd_soc_component_read32(component, WM1811_JACKDET_CTRL);
4086
+		ret = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
39454087 		if (ret < 0) {
39464088 			dev_err(component->dev, "Failed to read jack status: %d\n",
39474089 				ret);
....@@ -4234,6 +4376,14 @@
42344376 				    wm8994_vu_bits[i].mask,
42354377 				    wm8994_vu_bits[i].mask);
42364378 
4379
+	if (control->type != WM1811) {
4380
+		for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++)
4381
+			snd_soc_component_update_bits(component,
4382
+					wm8994_adc2_dac2_vu_bits[i].reg,
4383
+					wm8994_adc2_dac2_vu_bits[i].mask,
4384
+					wm8994_adc2_dac2_vu_bits[i].mask);
4385
+	}
4386
+
42374387 	/* Set the low bit of the 3D stereo depth so TLV matches */
42384388 	snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
42394389 			    1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
....@@ -4470,6 +4620,7 @@
44704620 static int wm8994_probe(struct platform_device *pdev)
44714621 {
44724622 	struct wm8994_priv *wm8994;
4623
+	int ret;
44734624 
44744625 	wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
44754626 			      GFP_KERNEL);
....@@ -4481,11 +4632,25 @@
44814632 
44824633 	wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
44834634 
4635
+	wm8994->mclk[WM8994_MCLK1].id = "MCLK1";
4636
+	wm8994->mclk[WM8994_MCLK2].id = "MCLK2";
4637
+
4638
+	ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk),
4639
+					 wm8994->mclk);
4640
+	if (ret < 0) {
4641
+		dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret);
4642
+		return ret;
4643
+	}
4644
+
44844645 	pm_runtime_enable(&pdev->dev);
44854646 	pm_runtime_idle(&pdev->dev);
44864647 
4487
-	return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
4648
+	ret = devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
44884649 			wm8994_dai, ARRAY_SIZE(wm8994_dai));
4650
+	if (ret < 0)
4651
+		pm_runtime_disable(&pdev->dev);
4652
+
4653
+	return ret;
44894654 }
44904655 
44914656 static int wm8994_remove(struct platform_device *pdev)